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* ********************************************************* */




#ifndef DSPMMU_H
#define DSPMMU_H

// MMU Control Register Addresses
#define PREFETCH_REG 	*((volatile unsigned short *) 0xFFFED200) // Prefetch register
#define WALKING_ST_REG	*((volatile unsigned short *) 0xFFFED204) // Prefetch status register
#define CNTL_REG		*((volatile unsigned short *) 0xFFFED208) // Control register	
#define FAULT_AD_H_REG	*((volatile unsigned short *) 0xFFFED20C) // Fault address register MSB
#define FAULT_AD_L_REG	*((volatile unsigned short *) 0xFFFED210) // Fault address register LSB	
#define F_ST_REG		*((volatile unsigned short *) 0xFFFED214) // Fault status register	
#define IT_ACK_REG		*((volatile unsigned short *) 0xFFFED218) // shorterrupt acknowledge register	
#define TTB_H_REG		*((volatile unsigned short *) 0xFFFED21C) // TTB register MSB	
#define TTB_L_REG		*((volatile unsigned short *) 0xFFFED220) // TTB register LSB	
#define LOCK_REG		*((volatile unsigned short *) 0xFFFED224) // Lock counter	
#define LD_TLB_REG		*((volatile unsigned short *) 0xFFFED228) // Load entry in TLB	
#define CAM_H_REG		*((volatile unsigned short *) 0xFFFED22C) // CAM entry register MSB	
#define CAM_L_REG		*((volatile unsigned short *) 0xFFFED230) // CAM entry register LSB	
#define RAM_H_REG		*((volatile unsigned short *) 0xFFFED234) // RAM entry register MSB	
#define RAM_L_REG		*((volatile unsigned short *) 0xFFFED238) // RAM entry register LSB	
#define GFLUSH_REG		*((volatile unsigned short *) 0xFFFED23C) // Global flush register	
#define FLUSH_ENTRY_REG	*((volatile unsigned short *) 0xFFFED240) // Individual flush register	
#define READ_CAM_H_REG	*((volatile unsigned short *) 0xFFFED244) // Read CAM register MSB
#define READ_CAM_L_REG	*((volatile unsigned short *) 0xFFFED248) // Read CAM register LSB
#define READ_RAM_H_REG	*((volatile unsigned short *) 0xFFFED24C) // Read RAM	register MSB
#define READ_RAM_L_REG	*((volatile unsigned short *) 0xFFFED250) // Read RAM	register LSB

// Endianess Control Register
#define MMU_EN_CTRL_REG *((volatile unsigned short *) 0xFFFECC34) // Endianess Control

// Parameters

// Entry Types
#define SECTION 	0x0
#define LARGE_PAGE	0x1
#define SMALL_PAGE	0x2
#define TINY_PAGE	0x3

// Access Permissions (Bits 9 and 8 of RAM_L_REG)
#define NO_ACCESS	0x000
#define READ_ONLY	0x200
#define READ_WRITE	0x300

// Entry Parameters (Bits 3 and 2 of RAM_L_REG)
#define PRESERVED	0x8
#define VALID		0x4

// TLB Operations
#define READ		0x2
#define	WRITE		0x1

// MMU Control
#define RESET		0x0
#define REL_RESET	0x1
#define	ENABLE		0x2
#define DISABLE		0xFFFD
#define	USE_TABLE	0x4

// Interrupt Acknowledge
#define ACKNOWLEDGE 0x1

typedef struct TLBENTRY
{
 int VirtualAddress;
 int PhysicalAddress;
 short Type;
 short AccessPermission;
} TLB_ENTRY;


#endif