?? combi.lst
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CYPRESS "C" COMPILER V1.07c 13-Jul-2000 PAGE 1
/*
**
** FILE: combi.c
**
**
** purpose: USB firmware for Cypress USB/PS2 mouse reference design
**
**
** revision history:
** 6/27/00 bth : modified ps2 scaling algorithm
** 7/11/00 sea : modified ps2 resolution constants and
** ps2_send() start bit inhibit response
**
*/
#pragma option INSTRUCTIONTIMING //needed for Cypress debugger to work properly
#pragma option f0 //do not insert page breaks in listing file
#pragma option REGSAVEOFF; //do not automatically save AC and IX in interrupts
#pragma option NOINIT;
0006 #define DEBUG
#include "chip.h"
/***
HEADER FOR CYPRESS 637XX
***/
#ifndef __CYC_H
0007 #define __CYC_H
#pragma has BCPU;
0000 registera AC;
0000 registerx IX;
0000 registercc CC; /* CC.Z : Zero Flag, CC.C : Carry Flag */
0008 #define ENDPOINT_A2_FIFO_SIZE 0x08
00E8 #define ENDPOINT_A2_ADDRESS 0xE8
00E8 0008 unsigned char ENDPOINT_A2_FIFO[ENDPOINT_A2_FIFO_SIZE] @ ENDPOINT_A2_ADDRESS;
0008 #define ENDPOINT_A1_FIFO_SIZE 0x08
00F0 #define ENDPOINT_A1_ADDRESS 0xF0
00F0 0008 unsigned char ENDPOINT_A1_FIFO[ENDPOINT_A1_FIFO_SIZE] @ ENDPOINT_A1_ADDRESS;
0008 #define ENDPOINT_A0_FIFO_SIZE 0x08
00F8 #define ENDPOINT_A0_ADDRESS 0xF8
00F8 0008 unsigned char ENDPOINT_A0_FIFO[ENDPOINT_A0_FIFO_SIZE] @ ENDPOINT_A0_ADDRESS;
0018 #define USB_FIFO_SIZE 0x18
0100 #define RAM_SIZE 0x100 /* 0x00 - 0xff */
0000 #define RAM_START 0x00
#ifndef STACK_SIZE
0030 #define STACK_SIZE 0x30
#endif /* STACK_SIZE */
0000 #define STACK_START RAM_START
0030 #define REGISTER_START RAM_START+STACK_SIZE
00B8 #define REGISTER_SIZE RAM_SIZE-USB_FIFO_SIZE-STACK_SIZE
0004 #define SPAD_SIZE 4
0030 00B8 #pragma memory RAM [REGISTER_SIZE] @ REGISTER_START;
#ifndef NOLOCAL
00E4 0000 #pragma memory LOCAL[0] @ REGISTER_START+REGISTER_SIZE-SPAD_SIZE;
#endif /* NOLOCAL */
0000 0031 #pragma memory STACK[ STACK_SIZE +1 ] @ RAM_START;
1800 #define ROM_SIZE 0x1800 /* 6K bytes */
0020 #define ROM_START 0x0020 /* after interrupt vectors */
0020 #define ROM_RESERVED 32
0020 17C0 #pragma memory ROM[ROM_SIZE-ROM_RESERVED-ROM_START] @ ROM_START;
0000 #define USB_bmRequestType 0
0001 #define USB_bRequest 1
0002 #define USB_wValue 2
0003 #define USB_wValueHi 3
0004 #define USB_wIndex 4
0005 #define USB_wIndexHi 5
0006 #define USB_wLength 6
0007 #define USB_wLengthHi 7
0000 #pragma vector MY_RESET_ISR @ 0x0000; /* reset vector */
0002 #pragma vector USB_BUS_RESET_ISR @ 0x0002; /* usb reset isr */
0004 #pragma vector MICROSECONDx128_ISR @ 0x0004; /* 128us interrupt */
0006 #pragma vector MILLISECOND_ISR @ 0x0006; /* 1.024ms interrupt */
0008 #pragma vector USB_A_EP0_ISR @ 0x0008; /* endpoint 0 interrupt */
000A #pragma vector USB_A_EP1_ISR @ 0x000A; /* endpoint 1 interrupt */
000C #pragma vector USB_A_EP2_ISR @ 0x000C; /* endpoint 2 interrupt */
000E #pragma vector USB_SPI_ISR @ 0x000E; /* spi interrupt */
0010 #pragma vector USB_CAPA_ISR @ 0x0010; /* capture timer a interrupt*/
0012 #pragma vector USB_CAPB_ISR @ 0x0012; /* capture timer b interrupt*/
0014 #pragma vector GPIO_ISR @ 0x0014; /* GPIO interrupt */
0016 #pragma vector WAKEUP_ISR @ 0x0016; /* wakeup timer interrupt */
00FF #pragma portrw PROCESSOR_STATUS @ 0xff; /* processor status and control */
0007 #define IRQ_PENDING 7
0006 #define WATCHDOG_RESET 6
0005 #define USB_RESET 5
0004 #define POWERON_RESET 4
0003 #define SUSPEND 3
0002 #define INTERRUPT_MASK 2
0001 #define SINGLE_STEP 1
0000 #define RUN 0
00F8 #pragma portrw CLOCK_CONFIGURATION @0xf8;
0008 #define PRECISION_USB_CLOCKING (1 << 2)
0009 #define TWAKEUP_MASK (7 << 4)
000A #define TWAKEUP_2 (1 << 4)
000B #define TWAKEUP_64 ( 6 << 4)
000C #define TWAKEUP_MAX (7 << 4)
0000 #define TWAKEUP_MIN 0
0000 #pragma portrw PORT0 @ 0x00; /* GPIO data port 0 */
0001 #pragma portrw PORT1 @ 0x01; /* GPIO data port 1 */
0002 #pragma portrw PORT2 @ 0x02; /* aux port*/
0004 #pragma portw PORT0IE @ 0x04; /* Interrupt enable for Port 0 */
0005 #pragma portw PORT1IE @ 0x05; /* Interrupt enable for Port 1 */
0006 #pragma portw PORT0IP @ 0x06; /* Interrupt polarity for Port 0 */
0007 #pragma portw PORT1IP @ 0x07; /* Interrupt polarity for Port 1 */
000A #pragma portrw PORT0_MODE0 @ 0x0A;
000B #pragma portrw PORT0_MODE1 @ 0x0B;
000C #pragma portrw PORT1_MODE0 @ 0x0C;
000D #pragma portrw PORT1_MODE1 @ 0x0D;
0010 #pragma portrw USB_DEVICE_A @ 0x10; /* USB device address */
0011 #pragma portrw EP_A0_COUNTER @ 0x11; /* endpoint 0 counter */
0012 #pragma portrw EP_A0_MODE @ 0x12; /* endpoint 0 configuration */
0013 #pragma portrw EP_A1_COUNTER @ 0x13; /* endpoint 1 counter */
0014 #pragma portrw EP_A1_MODE @ 0x14; /* endpoint 1 configuration */
0015 #pragma portrw EP_A2_COUNTER @ 0x15; /* endpoint 2 counter */
0016 #pragma portrw EP_A2_MODE @ 0x16; /* endpoint 2 configuration */
0007 #define DEVICE_ADDRESS_ENABLE 7 /* bit 7 of USB_DEVICE*/
0007 #define SETUP_RECEIVED 7
0006 #define IN_RECEIVED 6
0005 #define OUT_RECEIVED 5
0004 #define ACKNOWLEDGE 4
0000 #define USB_MODE_DISABLE 0b0000
0001 #define USB_MODE_NAK_IN_OUT 0b0001
0002 #define USB_MODE_STATUS_OUT 0b0010
0003 #define USB_MODE_STALL_IN_OUT 0b0011
0004 #define USB_MODE_IGNORE_IN_OUT 0b0100
0005 #define USB_MODE_ISOCHRONOUS_OUT 0b0101
0006 #define USB_MODE_STATUS_ONLY 0b0110
0007 #define USB_MODE_ISOCHRONOUS_IN 0b0111
0008 #define USB_MODE_NAK_OUT 0b1000
0009 #define USB_MODE_ACK_OUT 0b1001
000A #define USB_MODE_NAK_OUT_STATUS_IN 0b1010
000B #define USB_MODE_ACK_OUT_STATUS_IN 0b1011
000C #define USB_MODE_NAK_IN 0b1100
000D #define USB_MODE_ACK_IN 0b1101
000E #define USB_MODE_NAK_IN_STATUS_OUT 0b1110
000F #define USB_MODE_ACK_IN_STATUS_OUT 0b1111
000F #define USB_MODE_MASK 0b1111
0020 #pragma portrw GLOBAL_INTERRUPT @ 0x20; /* Global interrupt enable */
0000 #define DISABLE_INTERRUPTS 0b00000000
0080 #define WAKEUP_ENABLE 0b10000000
0040 #define GPIO_ENABLE 0b01000000
0008 #define I2C_ENABLE 0b00001000
0004 #define MILLISECOND_ENABLE 0b00000100
0002 #define MICROSECOND_ENABLE 0b00000010
0001 #define USB_BUS_RESET_ENABLE 0b00000001
0021 #pragma portrw ENDPOINT_INTERRUPT @ 0x21; /* USB endpoint interrupt enable */
0004 #define EPA2_ENABLE 0b00100
0002 #define EPA1_ENABLE 0b00010
0001 #define EPA0_ENABLE 0b00001
0024 #pragma portr TIMER @ 0x24; /* lower eight bits of timer */
0024 #pragma portr TIMER_LSB @ 0x24; /* lower eight bits of timer */
0025 #pragma portr TIMER_MSB @ 0x25; /* upper six bits of timer */
0026 #pragma portrw WATCHDOG @ 0x26; /* watchdog timer */
001F #pragma portrw USB_STATUS @ 0x1F; /* USB upstream status and control */
000D #define VREG_ENABLE_MASK (1 << 6)
000E #define PS2_PULLUP_MASK (1 << 7)
000F #define PS2_INTERRUPT_MODE_MASK (1 << 5)
0010 #define BUS_ACTIVITY_MASK (1 << 3)
0003 #define BUS_ACTIVITY 3
0000 #define NOT_FORCING 0b000
0001 #define FORCE_K 0b001
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