#pragma once

////////////////////////////////////////////////////////////////////////////////
//
//	DebugZones shared by both MDD & PDD. PDD takes zone 8..13
//

#ifdef DEBUG
#define ZONE_INIT		DEBUGZONE(0)
#define ZONE_OPEN		DEBUGZONE(1)
#define ZONE_READ		DEBUGZONE(2)
#define ZONE_WRITE		DEBUGZONE(3)
#define ZONE_CLOSE		DEBUGZONE(4)
#define ZONE_IOCTL		DEBUGZONE(5)
#define ZONE_THREAD		DEBUGZONE(6)
#define ZONE_EVENTS		DEBUGZONE(7)
#define ZONE_CRITSEC	DEBUGZONE(8)
#define ZONE_FLOW		DEBUGZONE(9)
#define ZONE_IR			DEBUGZONE(10)
#define ZONE_USR_READ	DEBUGZONE(11)
#define ZONE_ALLOC		DEBUGZONE(12)
#define ZONE_FUNCTION	DEBUGZONE(13)
#define ZONE_WARN		DEBUGZONE(14)
#define ZONE_ERROR		DEBUGZONE(15)

// DEBUGZONE(8..13) are for PDD.

#define ZONE_WARNING	DEBUGZONE(14)
#define ZONE_ERROR		DEBUGZONE(15)

// NOTE:  One file should use INSTANTIATE_GPE_ZONES.  This allows it to be 
// pre-compiled initialZones should typically be 0x0003
// modname is a string such as "DDI driver"
// opt1 and 2 are user defined (device-specific) zones e.g. "Reg0 Write"

#define INSTANTIATE_CAN_ZONES(initialZones, modname)	\
DBGPARAM dpCurSettings =                                \
{                                                       \
    TEXT(modname),                                      \
    {                                                   \
        TEXT("Init"),                   /* 0  */        \
        TEXT("Open"),                   /* 1  */        \
        TEXT("Read"),                   /* 2  */        \
        TEXT("Write"),                  /* 3  */        \
        TEXT("Close"),                  /* 4  */        \
        TEXT("Ioctl"),                  /* 5  */        \
        TEXT("Thread"),                 /* 6  */        \
        TEXT("Events"),                 /* 7  */        \
        TEXT("CritSec"),                /* 8  */        \
        TEXT("FlowCtrl"),               /* 9  */        \
        TEXT("Infrared"),               /* 10 */        \
        TEXT("User Read"),              /* 11 */        \
        TEXT("Alloc"),                  /* 12 */        \
        TEXT("Function"),               /* 13 */        \
        TEXT("Warning"),                /* 14 */        \
        TEXT("Error"),                  /* 15 */        \
    },                                                  \
    (initialZones)                                      \
};
#else    // NOT DEBUG

#define INSTANTIATE_CAN_ZONES(initialZones, modname)

#endif

////////////////////////////////////////////////////////////////////////////////


/* register offsets from base address for the SJA1000 */

#define MOD		0x00		/* mode & control register */
#define CMR		0x01		/* command register */
#define SR		0x02		/* status register */
#define IR		0x03		/* interrupt register */
#if defined (SJA1000_PELICAN_MODE)
#define IER		0x04		/* interrupt enable register */
#else /* BasicCAN mode */
#define IER		0x00
#endif
#define BTR0	0x06		/* bus timing register 0 */
#define BTR1	0x07		/* bus timing register 1 */
#define OCR		0x08		/* output control register */
#define TST		0x09
#define ALC		0x0B		/* arbitration lost capture register */
#define ECC		0x0C		/* error code capture register */
#define EWL		0x0D		/* error warning limit register */
#define RXERR	0x0E		/* rx error counter register */
#define TXERR	0x0F		/* tx error counter register */
#define ACR		0x10		/* acceptance code register */
#define MCR		0x14		/* acceptance mask register */
#define RMC		0x1D		/* rx message counter */
#define RBSA	0x1E		/* rx buffer start address register */
#define CDR		0x1F		/* clock divider register */

/* address definitions of the Rx-Buffer */

#if defined (SJA1000_PELICAN_MODE)
#define RXINFO	16
#define RXBUF	17
#else /* BasicCAN mode */
#define RXBUF	20
#endif

/* address definitions of the Tx-Buffer */

#if defined (SJA1000_PELICAN_MODE)
/* write only addresses */
#define TXINFO	16
#define TXBUF	17
#else /* BasicCAN mode */
#define TXBUF	10
#endif

/* address and bit definitions for the MODE & CONTROL REGISTER */

#define MOD_RM		0x01	/* reset mode (request) bit */
#if defined (SJA1000_PELICAN_MODE)
#define MOD_LOM		0x02	/* listen only mode bit */
#define MOD_STM		0x04	/* self test mode bit */
#define MOD_AFM		0x08	/* acceptance filter mode bit */
#define MOD_SM		0x10	/* enter sleep mode bit */
#endif

/* address and bit definitions for the COMMAND REGISTER */

#define CMR_TR		0x01	/* transmission request bit */
#define CMR_AT		0x02	/* abort transmission bit */
#define CMR_RRB		0x04	/* release receive buffer bit */
#define CMR_CDO		0x08	/* clear data overrun bit */
#if defined (SJA1000_PELICAN_MODE)
#define CMR_SRR		0x10	/* self reception request bit */
#else /* BasicCAN mode */
#define CMR_GTS		0x10	/* goto sleep bit (BasicCAN mode) */
#endif

/* address and bit definitions for the STATUS REGISTER */

#define SR_RBS		0x01	/* receive buffer status bit */
#define SR_DOS		0x02	/* data overrun status bit */
#define SR_TBS		0x04	/* transmit buffer status bit */
#define SR_TCS		0x08	/* transmission complete status bit */
#define SR_RS		0x10	/* receive status bit */
#define SR_TS		0x20	/* transmit status bit */
#define SR_ES		0x40	/* error status bit */
#define SR_BS		0x80	/* bus status bit */

/* address and bit definitions for the INTERRUPT REGISTER */

#define IR_RI		0x01	/* receive interrupt bit */
#define IR_TI		0x02	/* transmit interrupt bit */
#define IR_EI		0x04	/* error warning interrupt bit */
#define IR_DOI		0x08	/* data overrun interrupt bit */
#define IR_WUI		0x10	/* wake-up interrupt bit */
#if defined (SJA1000_PELICAN_MODE)
#define IR_EPI		0x20	/* error passive interrupt bit */
#define IR_ALI		0x40	/* arbitration lost interrupt bit */
#define IR_BEI		0x80	/* bus error interrupt bit */
#endif

/* address and bit definitions for the
							INTERRUPT ENABLE & CONTROL REGISTER */

#if defined (SJA1000_PELICAN_MODE)
#define IER_RIE		0x01	/* receive interrupt enable bit */
#define IER_TIE		0x02	/* transmit interrupt enable bit */
#define IER_EIE		0x04	/* error warning interrupt enable bit */
#define IER_DOIE	0x08	/* data overrun interrupt enable bit */
#define IER_WUIE	0x10	/* wake-up interrupt enable bit */
#define IER_EPIE	0x20	/* error passive interrupt enable bit */
#define IER_ALIE	0x40	/* arbitration lost interr. enable bit*/
#define IER_BEIE	0x80	/* bus error interrupt enable bit */
#else /* BasicCAN mode */
#define IER_RIE		0x02	/* Receive Interrupt enable bit */
#define IER_TIE		0x04	/* Transmit Interrupt enable bit */
#define IER_EIE		0x08	/* Error Interrupt enable bit */
#define IER_DOIE	0x10	/* Overrun Interrupt enable bit */
#endif

/* address and bit definitions for the BUS TIMING REGISTERS */

#define BTR_SAM 0x80 /* sample mode bit
						1 == the bus is sampled 3 times
						0 == the bus is sampled once */

/* address and bit definitions for the OUTPUT CONTROL REGISTER */

#define OCMODE0		0x00	/* Output Control Mode 0 */
#define OCMODE1		0x01	/* Output Control Mode 1 */
/* Interpretation of OCMODE bits */
#define	OCMODE_BIPHASE	0		/* bi-phase output mode */
#define	OCMODE_TEST		1		/* test output mode */
#define	OCMODE_NORMAL	2		/* normal output mode */
#define	OCMODE_CLOCK	3		/* clock output mode */

#define OCPOL0		0x02	/* Output Control Polarity 1 */
#define OCTN0		0x03	/* Output Control Transistor P0 */
#define OCTP0		0x04	/* Output Control Transistor N0 */
#define OCPOL1		0x05	/* Output Control Polarity 0 */
#define OCTN1		0x06	/* Output Control Transistor P1 */
#define OCTP1		0x07	/* Output Control Transistor N1 */
/* Output pin configuration */
#define	OC_FLOAR		0		/* 配置為懸空 */
#define	OC_PULLDOWN		2		/* 配置為下拉 */
#define	OC_PULLUP		4		/* 配置為上拉 */
#define	OC_PUSHPULL		6		/* 配置為推挽 */

#define	TX0_FLOAR		(OC_FLOAR << 2)
#define	TX0_PULLDOWN	(OC_PULLDOWN << 2)
#define	TX0_PULLUP		(OC_PULLUP << 2)
#define	TX0_PUSHPULL	(OC_PUSHPULL << 2)

#define	TX1_FLOAR		(OC_FLOAR << 5)
#define	TX1_PULLDOWN	(OC_PULLDOWN << 5)
#define	TX1_PULLUP		(OC_PULLUP << 5)
#define	TX1_PUSHPULL	(OC_PUSHPULL << 5)

/* Arbitration Lost Capture Register */

/* Error Code Capture Register */
/* Error Warning Limit Register */
/* Rx Error Counter Register */
/* Tx Error Counter Register */

/* address definitions of ACCEPTANCE CODE & MASK REGISTERS */

/* Rx Message Counter */
/* Rx Buffer Start Address Register */

/* address and bit definitions for the CLOCK DIVIDER REGISTER */

#define	CDR_CLKOFF		0x08		/* disable the external CLKOUT pin */
#define	CDR_RXINTEN		0x20		/* use the TX1 output as a dedicated 
									   receive interrupt output */
#define	CDR_CBP			0x40		/* bypass the CAN input comparator */
#define	CDR_PELICAN		0x80		/* set to logic 1 the CAN controller 
								       operates in PeliCAN mode */

#define IOCTL_SET_CAN_BAUD			0x01
#define IOCTL_SET_CAN_TXMODE		0x02
#define IOCTL_SET_CAN_FILTER		0x03

/* can message structure */

typedef	 struct {	/* CAN_MSG */
	union {
		UINT8	id[4];
		UINT32	identifier;	
	};
	union {
		struct {
		UINT8	length	:4;		/* data length */
		UINT8	resbit	:2;
		UINT8	remote	:1;		/* remote transmission request */
		UINT8	format	:1;		/* frame format */
		};
		UINT8	info;
	};
	UINT8	reserve[3];
	UINT8	data[8];			/* data field */
} CAN_MSG;



void SJA1000_ReadRegister(UINT8 reg, UINT8 *value);
void SJA1000_WriteRegister(UINT8 reg, UINT8 value);
void SJA1000_Init();
void SJA1000_SetFilter(UINT32 ACRCode, UINT32 AMRCode);
void SJA1000_BaudSet(UINT8 BTR[]);
void SJA1000_MsgWrite(CAN_MSG *pMsg);
void SJA1000_MsgRead(CAN_MSG *pMsg);


VOID EINT_ConfigInterruptPin(VOID);
BOOL EINT_InitializeAddresses(VOID);
BOOL CAN_InitializeAddresses(VOID);

static DWORD WINAPI CAN_IntrThread(LPVOID pContext);