?? regmapo.h
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// GROUP 36
UINT32 g36_reserved[32]; // 00 1152~1183 (1200) $bffe9200
// GROUP 37
UINT32 g37_reserved[32]; // 00 1184~1215 (1280) $bffe9280
// GROUP 38
UINT32 g38_reserved[32]; // 00 1216~1247 (1300) $bffe9300
// GROUP 39
UINT32 g39_reserved[32]; // 00 1248~1279 (1380) $bffe9380
// GROUP 40: (EMU) SDRAM 6B
UINT32 sdc_req_t_reset; // 00 1280 (1400) $bffe9400
UINT32 sdc_req_time[14][2]; // 01 1281~1308
UINT32 g40_reserved[3]; // 1d 1309~1311 (1474)
// GROUP 41: (EMU) SDRAM 6A
UINT32 sdc_data_cnt[14][2]; // 00 1312~1339 (0520) $bffe9480
UINT32 sdc_n_req_cnt[2]; // 1c 1340~1341 (14f0)
UINT32 sdc_cke_cnt[2]; // 1e 1342~1343 (14f8)
// GROUP 42~49
UINT32 g42_reserved[32]; // 00 1344~1375 (1500) $bffe9500
UINT32 g43_reserved[32]; // 00 1376~1407 (1580) $bffe9580
UINT32 g44_reserved[32]; // 00 1408~1439 (1600) $bffe9600
UINT32 g45_reserved[32]; // 00 1440~1471 (1680) $bffe9680
UINT32 g46_reserved[32]; // 00 1472~1503 (1700) $bffe9700
UINT32 g47_reserved[32]; // 00 1504~1535 (1780) $bffe9780
UINT32 g48_reserved[32]; // 00 1536~1567 (1800) $bffe9800
UINT32 g49_reserved[32]; // 00 1568~1599 (1880) $bffe9880
// GROUP 50
UINT32 g50_reserved[29]; // 00 1600~1628 (1900) $bffe9900
UINT32 risc_fpga_version[3]; // 1d 1629~1631 (1974)
// GROUP 51
UINT32 g51_reserved[29]; // 00 1632~1660 (1980) $bffe9980
UINT32 block_fpga_version[3]; // 1d 1661~1663 (19f4)
// GROUP 52
UINT32 g52_reserved[29]; // 00 1664~1692 (1a00) $bffe9a00
UINT32 aud_fpga_version[3]; // 1d 1693~1695 (1a74)
// GROUP 53~63
UINT32 g53_reserved[32]; // 00 1696~1727 (1a80) $bffe9a80
UINT32 g54_reserved[32]; // 00 1728~1759 (1b00) $bffe9b00
UINT32 g55_reserved[32]; // 00 1760~1791 (1b80) $bffe9b80
UINT32 g56_reserved[32]; // 00 1792~1823 (1c00) $bffe9c00
UINT32 g57_reserved[32]; // 00 1824~1855 (1c80) $bffe9c80
UINT32 g58_reserved[32]; // 00 1856~1887 (1d00) $bffe9d00
UINT32 g59_reserved[32]; // 00 1888~1919 (1d80) $bffe9d80
UINT32 g60_reserved[32]; // 00 1920~1951 (1e00) $bffe9e00
UINT32 g61_reserved[32]; // 00 1952~1983 (1e80) $bffe9e80
UINT32 g62_reserved[32]; // 00 1984~2015 (1f00) $bffe9f00
UINT32 g63_reserved[32]; // 00 2016~2047 (1f80) $bffe9f80
// GROUP 64~255
UINT32 gxx_reserved[192][32]; // 00 2048~8191 (0800) $bffea000
// GROUP
WorkBuf reg_dma_buf;
WorkBuf reg_dma_buf256;
WorkBuf reg_dma_buf512;
WorkBuf reg_dma_buf768;
//
// (OLD hardware, just for compatible issue)
//
// UINT32 evbya2; // 00 8192 (8000) $bfff0000
// UINT32 eabya; // 01 8193 (8004)
// UINT32 dsp16ya; // 02 8194 (8008)
// UINT32 dma_addrmode; // 03 8195 (800c)
// UINT32 dma_addrlen; // 04 8196 (8010)
// UINT32 epp_status; // 05 8197 (8014)
// UINT32 epp_data; // 06 8198 (8018)
// UINT32 agdc_config; // 07 8199 (801c)
// UINT32 video_compress; // 08 8200 (8020)
// UINT32 dis_tv_out; // 09 8201 (8024)
// UINT32 audio_clkgen; // 05 5 (0014)
} RegisterFile;
/*
** Video
*/
#define RF_CODING_EXT0_PROGRESSIVE_FRAME (1<<0)
#define RF_CODING_EXT0_CHROMA_420_TYPE (1<<1)
#define RF_CODING_EXT0_REPEAT_FIRST_FIELD (1<<2)
#define RF_CODING_EXT0_ALTERNATE_SCAN (1<<3)
#define RF_CODING_EXT0_INTRA_VLC_FORMAT (1<<4)
#define RF_CODING_EXT0_Q_SCALE_TYPE (1<<5)
#define RF_CODING_EXT0_CONCEAL_MOTION_VECTORS (1<<6)
#define RF_CODING_EXT0_FRAME_PRED_FRAME_DCT (1<<7)
#define RF_CODING_EXT0_TOP_FIELD_FIRST (1<<8)
#define RF_CODING_EXT0_PICTURE_STRUCTURE (0x03<<9)
#define RF_CODING_EXT0_INTRA_DC_PRECISION (0x03<<11)
//#define RF_CODING_EXT0_LAST_PICTURE (1<<14)
#define RF_CODING_EXT0_BACK_LAST (1<<14)
#define RF_CODING_EXT0_SECOND_FIELD (1<<15)
#define ext0_pic_struct(x) (((x)>>9)&0x03)
/*
** Display Output Tweaking
*/
#define RF_VOUT_SWAP_CBCR (1<<1)
#define RF_VOUT_SWAP_LC (1<<2)
/*
** Display Status
*/
#define RF_Display_OSDRegion 0x00ff
#define RF_Display_FieldNo 0x8000
#define RF_Display_VSyncB 0x4000
#define RF_Display_HSyncB 0x2000
#define RF_Display_FieldEnd 0x1000
#define DISPLAY_STATUS regs0->osd_display_status
#define IsVSync() ((DISPLAY_STATUS & RF_Display_VSyncB)==0)
#define IsHSync() ((DISPLAY_STATUS & RF_Display_HSyncB)==0)
#define IsTopField() ((DISPLAY_STATUS & RF_Display_FieldNo)==0)
#define IsBottomField() ((DISPLAY_STATUS & RF_Display_FieldNo))
#define IsFieldEnd() ((DISPLAY_STATUS & RF_Display_FieldEnd))
#define RF_Video_VPicEnd 0x0001
#define RF_Video_VTblErr 0x0002
#define RF_Video_VRunErr 0x0004
#define RF_Video_VSliceErr 0x0008
#define RF_Video_VErr 0x8000
/*
** RISC Picture Start
*/
#define IsRPicStart (regs0->pic_start)
/*
** VLD Decoding Status
*/
#define VLD_STATUS (regs0->vld_status)
#define IsVPicEnd (VLD_STATUS & RF_Video_VPicEnd)
#define IsVRunErr (VLD_STATUS & RF_Video_VRunErr)
#define IsVTblErr (VLD_STATUS & RF_Video_VTblErr)
#define IsVErr (VLD_STATUS & RF_Video_VErr)
#define RF_CODING_EXT1_FORWARD_REF0 (0<<1)
#define RF_CODING_EXT1_FORWARD_REF1 (1<<1)
#define RF_CODING_EXT1_RECONST_REF0 (0<<2)
#define RF_CODING_EXT1_RECONST_REF1 (1<<2)
#define RF_CODING_EXT1_RECONST_B (2<<2)
#define RF_CODING_EXT1_FIELDID (1<<4)
//
// TIMER TIMER TIMER TIMER TIMER TIMER TIMER
//
#define RF_TIMER_SRC_SYSCLK (0<<14)
#define RF_TIMER_SRC_STC (1<<14)
#define RF_TIMER_SRC_RTC (2<<14)
#define RF_TIMER_SRC_TIMER (3<<14)
#define RF_TIMER_RUN_ON (1<<13)
#define RF_TIMER_RUN_OFF (0<<13)
#define RF_TIMER_GO_ON (1<<11)
#define RF_TIMER_GO_OFF (0<<11)
#define RF_TIMER_MASK (0x3ff)
#define TIMER_CONFIG_STOP ( RF_TIMER_GO_OFF )
#define TIMER_CONFIG_STC ( RF_TIMER_SRC_STC \
| RF_TIMER_RUN_ON \
| RF_TIMER_GO_ON)
#define TIMER_CONFIG_10ms ( TIMER_CONFIG_STC | (900-1))
#define TIMER_CONFIG_4ms ( TIMER_CONFIG_STC | (360-1))
#define TIMER_CONFIG_1ms ( TIMER_CONFIG_STC | (90-1))
#define TIMER_CONFIG_dly ( RF_TIMER_SRC_STC \
| RF_TIMER_RUN_OFF \
| RF_TIMER_GO_ON)
#define TIMER_CONFIG_dlys(n) ( TIMER_CONFIG_dly | (n-1))
#define TIMER_CONFIG_90k(n) ( TIMER_CONFIG_STC | (n-1))
/*
** VPP VPP VPP VPP VPP VPP VPP
*/
#define RF_HFACTOR_HEXP_ENABLE (1<<8)
#define RF_HFACTOR_CIF_ENABLE (1<<9)
/*
** CDDSP Control/Status
*/
#define RF_CDDSP_RESET 0x0001
#define RF_CDDSP_STOP 0x0002
#define RF_CDDSP_PAUSE 0x0004
#define RF_CDDSP_SEEK 0x0008
#define RF_CDDSP_CRC_ERROR 0x0001
#define RF_CDDSP_CRC_ERROR_LAST 0x0002
#define RF_CDDSP_CRC_ERROR_MASK 0x0003
/*
**
*/
#define RF_DSP24_RESET (1<<0)
#define RF_DSP24_STALL (1<<1)
/*
** EPP status
*/
#define RF_EPP_IN_FULL (1<<3)
#define RF_EPP_IN_EMPTY (1<<2)
#define RF_EPP_OUT_FULL (1<<1)
#define RF_EPP_OUT_EMPTY (1<<0)
#define RF_Video_MPEG2_flag 0x08
/*
** AGDC config
*/
#define RF_AGDC_BPIC_LOC_RIGHT (0 << 0)
#define RF_AGDC_BPIC_LOC_BOTTOM (1 << 0)
#define RF_AGDC_BPIC_SIZE_LINE (0 << 2)
#define RF_AGDC_BPIC_SIZE_FIELD (1 << 2)
#define RF_AGDC_BPIC_SIZE_FULL (2 << 2)
#define RF_AGDC_SDRAM_64MB (0 << 6)
#define RF_AGDC_SDRAM_16MB (1 << 6)
#define set_dis_tv_std(n) (regs0->osd_tv_std=(n))
/*
** VIDEO VIDEO VIDEO VIDEO VIDEO VIDEO VIDEO VIDEO
*/
#define RF_COMPRESS_888 (0 << 0)
#define RF_COMPRESS_866 (1 << 0)
#define RF_COMPRESS_666 (2 << 0)
#define RF_COMPRESS_8655 (3 << 0)
#define RF_COMPRESS_DITHER_ON (1 << 7)
#define RF_COMPRESS_DITHER_OFF (0 << 7)
#define RF_COMPRESS_CHROMA_FULL (0 << 8)
#define RF_COMPRESS_CHROMA_HALF (1 << 8)
/*
** regs0: register file pointer
*/
#ifdef GLOBAL_REGISTER
register volatile RegisterFile *regs0 asm ("22");
#define InitRegFile() (regs0 = (volatile RegisterFile *)RGST_OFFSET)
#else
#define regs0 ((volatile RegisterFile *)RGST_OFFSET)
#define InitRegFile() {}
#endif
#endif/*__REGMAP_DVD_H*/
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