?? c8051f020.h
字號:
/* BIT Registers */
/* TCON 0x88 */
sbit TF1 = TCON ^ 7; /* TIMER 1 OVERFLOW FLAG */
sbit TR1 = TCON ^ 6; /* TIMER 1 ON/OFF CONTROL */
sbit TF0 = TCON ^ 5; /* TIMER 0 OVERFLOW FLAG */
sbit TR0 = TCON ^ 4; /* TIMER 0 ON/OFF CONTROL */
sbit IE1 = TCON ^ 3; /* EXT. INTERRUPT 1 EDGE FLAG */
sbit IT1 = TCON ^ 2; /* EXT. INTERRUPT 1 TYPE */
sbit IE0 = TCON ^ 1; /* EXT. INTERRUPT 0 EDGE FLAG */
sbit IT0 = TCON ^ 0; /* EXT. INTERRUPT 0 TYPE */
/* SCON0 0x98 */
sbit SM00 = SCON0 ^ 7; /* SERIAL MODE CONTROL BIT 0 */
sbit SM10 = SCON0 ^ 6; /* SERIAL MODE CONTROL BIT 1 */
sbit SM20 = SCON0 ^ 5; /* MULTIPROCESSOR COMMUNICATION ENABLE */
sbit REN0 = SCON0 ^ 4; /* RECEIVE ENABLE */
sbit TB80 = SCON0 ^ 3; /* TRANSMIT BIT 8 */
sbit RB80 = SCON0 ^ 2; /* RECEIVE BIT 8 */
sbit TI0 = SCON0 ^ 1; /* TRANSMIT INTERRUPT FLAG */
sbit RI0 = SCON0 ^ 0; /* RECEIVE INTERRUPT FLAG */
/* IE 0xA8 */
sbit EA = IE ^ 7; /* GLOBAL INTERRUPT ENABLE */
sbit ET2 = IE ^ 5; /* TIMER 2 INTERRUPT ENABLE */
sbit ES0 = IE ^ 4; /* UART0 INTERRUPT ENABLE */
sbit ET1 = IE ^ 3; /* TIMER 1 INTERRUPT ENABLE */
sbit EX1 = IE ^ 2; /* EXTERNAL INTERRUPT 1 ENABLE */
sbit ET0 = IE ^ 1; /* TIMER 0 INTERRUPT ENABLE */
sbit EX0 = IE ^ 0; /* EXTERNAL INTERRUPT 0 ENABLE */
/* IP 0xB8 */
sbit PT2 = IP ^ 5; /* TIMER 2 PRIORITY */
sbit PS = IP ^ 4; /* SERIAL PORT PRIORITY */
sbit PT1 = IP ^ 3; /* TIMER 1 PRIORITY */
sbit PX1 = IP ^ 2; /* EXTERNAL INTERRUPT 1 PRIORITY */
sbit PT0 = IP ^ 1; /* TIMER 0 PRIORITY */
sbit PX0 = IP ^ 0; /* EXTERNAL INTERRUPT 0 PRIORITY */
/* SMB0CN 0xC0 */
sbit BUSY = SMB0CN ^ 7; /* SMBUS 0 BUSY */
sbit ENSMB = SMB0CN ^ 6; /* SMBUS 0 ENABLE */
sbit STA = SMB0CN ^ 5; /* SMBUS 0 START FLAG */
sbit STO = SMB0CN ^ 4; /* SMBUS 0 STOP FLAG */
sbit SI = SMB0CN ^ 3; /* SMBUS 0 INTERRUPT PENDING FLAG */
sbit AA = SMB0CN ^ 2; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
sbit SMBFTE = SMB0CN ^ 1; /* SMBUS 0 FREE TIMER ENABLE */
sbit SMBTOE = SMB0CN ^ 0; /* SMBUS 0 TIMEOUT ENABLE */
/* T2CON 0xC8 */
sbit TF2 = T2CON ^ 7; /* TIMER 2 OVERFLOW FLAG */
sbit EXF2 = T2CON ^ 6; /* EXTERNAL FLAG */
sbit RCLK = T2CON ^ 5; /* RECEIVE CLOCK FLAG */
sbit TCLK = T2CON ^ 4; /* TRANSMIT CLOCK FLAG */
sbit EXEN2 = T2CON ^ 3; /* TIMER 2 EXTERNAL ENABLE FLAG */
sbit TR2 = T2CON ^ 2; /* TIMER 2 ON/OFF CONTROL */
sbit CT2 = T2CON ^ 1; /* TIMER OR COUNTER SELECT */
sbit CPRL2 = T2CON ^ 0; /* CAPTURE OR RELOAD SELECT */
/* PSW */
sbit CY = PSW ^ 7; /* CARRY FLAG */
sbit AC = PSW ^ 6; /* AUXILIARY CARRY FLAG */
sbit F0 = PSW ^ 5; /* USER FLAG 0 */
sbit RS1 = PSW ^ 4; /* REGISTER BANK SELECT 1 */
sbit RS0 = PSW ^ 3; /* REGISTER BANK SELECT 0 */
sbit OV = PSW ^ 2; /* OVERFLOW FLAG */
sbit F1 = PSW ^ 1; /* USER FLAG 1 */
sbit P = PSW ^ 0; /* ACCUMULATOR PARITY FLAG */
/* PCA0CN D8H */
sbit CF = PCA0CN ^ 7; /* PCA 0 COUNTER OVERFLOW FLAG */
sbit CR = PCA0CN ^ 6; /* PCA 0 COUNTER RUN CONTROL BIT */
sbit CCF4 = PCA0CN ^ 4; /* PCA 0 MODULE 4 INTERRUPT FLAG */
sbit CCF3 = PCA0CN ^ 3; /* PCA 0 MODULE 3 INTERRUPT FLAG */
sbit CCF2 = PCA0CN ^ 2; /* PCA 0 MODULE 2 INTERRUPT FLAG */
sbit CCF1 = PCA0CN ^ 1; /* PCA 0 MODULE 1 INTERRUPT FLAG */
sbit CCF0 = PCA0CN ^ 0; /* PCA 0 MODULE 0 INTERRUPT FLAG */
/* ADC0CN E8H */
sbit AD0EN = ADC0CN ^ 7; /* ADC 0 ENABLE */
sbit AD0TM = ADC0CN ^ 6; /* ADC 0 TRACK MODE */
sbit AD0INT = ADC0CN ^ 5; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
sbit AD0BUSY = ADC0CN ^ 4; /* ADC 0 BUSY FLAG */
sbit AD0CM1 = ADC0CN ^ 3; /* ADC 0 START OF CONVERSION MODE BIT 1 */
sbit AD0CM0 = ADC0CN ^ 2; /* ADC 0 START OF CONVERSION MODE BIT 0 */
sbit AD0WINT = ADC0CN ^ 1; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */
sbit AD0LJST = ADC0CN ^ 0; /* ADC 0 RIGHT JUSTIFY DATA BIT */
/* SPI0CN F8H */
sbit SPIF = SPI0CN ^ 7; /* SPI 0 INTERRUPT FLAG */
sbit WCOL = SPI0CN ^ 6; /* SPI 0 WRITE COLLISION FLAG */
sbit MODF = SPI0CN ^ 5; /* SPI 0 MODE FAULT FLAG */
sbit RXOVRN = SPI0CN ^ 4; /* SPI 0 RX OVERRUN FLAG */
sbit TXBSY = SPI0CN ^ 3; /* SPI 0 TX BUSY FLAG */
sbit SLVSEL = SPI0CN ^ 2; /* SPI 0 SLAVE SELECT */
sbit MSTEN = SPI0CN ^ 1; /* SPI 0 MASTER ENABLE */
sbit SPIEN = SPI0CN ^ 0; /* SPI 0 SPI ENABLE */
sbit P07 = P0 ^ 7;
sbit P06 = P0 ^ 6;
sbit P05 = P0 ^ 5;
sbit P04 = P0 ^ 4;
sbit P03 = P0 ^ 3;
sbit P02 = P0 ^ 2;
sbit P01 = P0 ^ 1;
sbit P00 = P0 ^ 0;
sbit P17 = P1 ^ 7;
sbit P16 = P1 ^ 6;
sbit P15 = P1 ^ 5;
sbit P14 = P1 ^ 4;
sbit P13 = P1 ^ 3;
sbit P12 = P1 ^ 2;
sbit P11 = P1 ^ 1;
sbit P10 = P1 ^ 0;
sbit P27 = P2 ^ 7;
sbit P26 = P2 ^ 6;
sbit P25 = P2 ^ 5;
sbit P24 = P2 ^ 4;
sbit P23 = P2 ^ 3;
sbit P22 = P2 ^ 2;
sbit P21 = P2 ^ 1;
sbit P20 = P2 ^ 0;
sbit P37 = P3 ^ 7;
sbit P36 = P3 ^ 6;
sbit P35 = P3 ^ 5;
sbit P34 = P3 ^ 4;
sbit P33 = P3 ^ 3;
sbit P32 = P3 ^ 2;
sbit P31 = P3 ^ 1;
sbit P30 = P3 ^ 0;
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