------------------------------------------------------------------------------------ Company: -- Engineer: -- -- Create Date:    16:21:34 10/22/2007 -- Design Name: -- Module Name:    rs_enc_m0 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: ---- Dependencies: ---- Revision: -- Revision 0.01 - File Created-- Additional Comments: ------------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity rs_enc_m0 is    Port ( x : in  STD_LOGIC_VECTOR (7 downto 0);           y : out  STD_LOGIC_VECTOR (7 downto 0));end rs_enc_m0;architecture Behavioral of rs_enc_m0 isbegin  process(x)  begin  		y(0) <= x(0) XOR x(3) XOR x(5) XOR x(6);		y(1) <= x(0) XOR x(1) XOR x(3) XOR x(4) XOR x(5) XOR x(7);		y(2) <= x(1) XOR x(2) XOR x(3) XOR x(4);		y(3) <= x(0) XOR x(2) XOR x(3) XOR x(4) XOR x(5);		y(4) <= x(0) XOR x(1) XOR x(3) XOR x(4) XOR x(5) XOR x(6);		y(5) <= x(0) XOR x(1) XOR x(2) XOR x(4) XOR x(5) XOR x(6) XOR x(7);		y(6) <= x(1) XOR x(2) XOR x(3) XOR x(5) XOR x(6) XOR x(7);		y(7) <= x(2) XOR x(4) XOR x(5) XOR x(7);		--y <= z;	end process;end Behavioral;