Analysis & Synthesis report for Block1
Mon Nov 26 13:35:05 2007
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. User-Specified and Inferred Latches
  9. Registers Removed During Synthesis
 10. General Register Statistics
 11. Inverted Register Statistics
 12. Multiplexer Restructuring Statistics (Restructuring Performed)
 13. Source assignments for notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1
 14. Source assignments for notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
 15. Source assignments for sld_hub:sld_hub_inst
 16. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
 17. Parameter Settings for User Entity Instance: kkk:inst|altpll:altpll_component
 18. Parameter Settings for User Entity Instance: notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component
 19. Parameter Settings for User Entity Instance: notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|sld_mod_ram_rom:mgl_prim2
 20. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 21. In-System Memory Content Editor Settings
 22. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Nov 26 13:35:05 2007    ;
; Quartus II Version          ; 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name               ; Block1                                   ;
; Top-level Entity Name       ; Block1                                   ;
; Family                      ; Cyclone                                  ;
; Total logic elements        ; 294                                      ;
; Total pins                  ; 6                                        ;
; Total virtual pins          ; 0                                        ;
; Total memory bits           ; 1,024                                    ;
; DSP block 9-bit elements    ; N/A until Partition Merge                ;
; Total PLLs                  ; 1                                        ;
; Total DLLs                  ; N/A until Partition Merge                ;
+-----------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                            ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                         ; Setting            ; Default Value      ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                         ; EP1C3T144C8        ;                    ;
; Top-level entity name                                                          ; Block1             ; Block1             ;
; Family name                                                                    ; Cyclone            ; Stratix II         ;
; Use Generated Physical Constraints File                                        ; Off                ;                    ;
; Use smart compilation                                                          ; Off                ; Off                ;
; Maximum processors allowed for parallel compilation                            ; 1                  ; 1                  ;
; Restructure Multiplexers                                                       ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                            ; Off                ; Off                ;
; Preserve fewer node names                                                      ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                      ; Off                ; Off                ;
; Verilog Version                                                                ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                   ; VHDL93             ; VHDL93             ;
; State Machine Processing                                                       ; Auto               ; Auto               ;
; Safe State Machine                                                             ; Off                ; Off                ;
; Extract Verilog State Machines                                                 ; On                 ; On                 ;
; Extract VHDL State Machines                                                    ; On                 ; On                 ;
; Ignore Verilog initial constructs                                              ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                                        ; On                 ; On                 ;
; Parallel Synthesis                                                             ; Off                ; Off                ;
; NOT Gate Push-Back                                                             ; On                 ; On                 ;
; Power-Up Don't Care                                                            ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                   ; Off                ; Off                ;
; Remove Duplicate Registers                                                     ; On                 ; On                 ;
; Ignore CARRY Buffers                                                           ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                         ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                          ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore LCELL Buffers                                                           ; Off                ; Off                ;
; Ignore SOFT Buffers                                                            ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                                 ; Off                ; Off                ;
; Optimization Technique -- Cyclone                                              ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70                 ; 70                 ;
; Auto Carry Chains                                                              ; On                 ; On                 ;
; Auto Open-Drain Pins                                                           ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                          ; Off                ; Off                ;
; Perform gate-level register retiming                                           ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax                         ; On                 ; On                 ;
; Auto ROM Replacement                                                           ; On                 ; On                 ;
; Auto RAM Replacement                                                           ; On                 ; On                 ;
; Auto Shift Register Replacement                                                ; Auto               ; Auto               ;