?? clock2.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock2 is
port(clkin:in std_logic;
clkout:buffer std_logic
);
end entity;
architecture arc of clock2 is
begin
process(clkin)
begin
if (clkin'event and clkin='1') then
clkout <= not clkout;
end if;
end process;
end arc;
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