LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Speakera IS
PORT ( clk : IN STD_LOGIC;
      Tone : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
      SpkS : OUT STD_LOGIC );
END;
ARCHITECTURE one OF Speakera IS
   SIGNAL PreCLK, FullSpkS : STD_LOGIC;
BEGIN

	DivideCLK : PROCESS(clk)
VARIABLE Count4 :integer range 0 to  16;
BEGIN
    if (clk'event and clk='1') then
    	if 	Count4>=15 then
    		Count4:=0;
    	else
    		Count4:=Count4+1;	
    	end if;
    	
    	case Count4 is
    		when 0 to 7 =>PreCLK<='0';
    		when others =>PreCLK<='1';
    	end case;    		
    end if;
  end process;



GenSpkS : PROCESS(PreCLK, Tone)-- 11位可預置計數器
VARIABLE Count11 : STD_LOGIC_VECTOR (10 DOWNTO 0);
BEGIN
  IF PreCLK'EVENT AND PreCLK = '1' THEN
        IF Count11 = 16#7FF# THEN 
                          Count11 := Tone ; 
                          FullSpkS <= '1';
        ELSE Count11 := Count11 + 1; 
              FullSpkS <= '0'; 
        END IF;
  END IF;
END PROCESS;

	




DelaySpkS : PROCESS(FullSpkS)--將輸出再2分頻，展寬脈沖，使揚聲器有足夠功率發音
VARIABLE Count2 : STD_LOGIC;
BEGIN
 IF FullSpkS'EVENT AND FullSpkS = '1' THEN 
                     Count2 := NOT Count2;
         IF Count2 = '1' THEN SpkS <= '1';
         ELSE SpkS <= '0'; 
         END IF;
 END IF;
END PROCESS;
END;