{ "Warning" "WTAN_FULL_MINIMUM_REQUIREMENTS_NOT_MET" "kkk:inst\|altpll:altpll_component\|_clk0 42 " "Warning: Can't achieve minimum setup and hold requirement kkk:inst\|altpll:altpll_component\|_clk0 along 42 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve minimum setup and hold requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "sld_hub:sld_hub_inst\|jtag_debug_mode altera_internal_jtag~TMSUTAP altera_internal_jtag~TCKUTAP -0.130 ns register " "Info: tsu for register \"sld_hub:sld_hub_inst\|jtag_debug_mode\" (data pin = \"altera_internal_jtag~TMSUTAP\", clock pin = \"altera_internal_jtag~TCKUTAP\") is -0.130 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.109 ns + Longest pin register " "Info: + Longest pin to register delay is 5.109 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TMSUTAP 1 PIN JTAG_X1_Y6_N1 23 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 23; PIN Node = 'altera_internal_jtag~TMSUTAP'" {  } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TMSUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.825 ns) + CELL(0.292 ns) 3.117 ns sld_hub:sld_hub_inst\|jtag_debug_mode~171 2 COMB LC_X18_Y8_N4 1 " "Info: 2: + IC(2.825 ns) + CELL(0.292 ns) = 3.117 ns; Loc. = LC_X18_Y8_N4; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode~171'" {  } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "3.117 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|jtag_debug_mode~171 } "NODE_NAME" } } { "c:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/quartus/libraries/megafunctions/sld_hub.vhd" 394 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.254 ns) + CELL(0.738 ns) 5.109 ns sld_hub:sld_hub_inst\|jtag_debug_mode 3 REG LC_X19_Y7_N3 2 " "Info: 3: + IC(1.254 ns) + CELL(0.738 ns) = 5.109 ns; Loc. = LC_X19_Y7_N3; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode'" {  } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "1.992 ns" { sld_hub:sld_hub_inst|jtag_debug_mode~171 sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } } { "c:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/quartus/libraries/megafunctions/sld_hub.vhd" 394 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.030 ns ( 20.16 % ) " "Info: Total cell delay = 1.030 ns ( 20.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.079 ns ( 79.84 % ) " "Info: Total interconnect delay = 4.079 ns ( 79.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "5.109 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|jtag_debug_mode~171 sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } } { "c:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus/bin/Technology_Viewer.qrui" "5.109 ns" { altera_internal_jtag~TMSUTAP {} sld_hub:sld_hub_inst|jtag_debug_mode~171 {} sld_hub:sld_hub_inst|jtag_debug_mode {} } { 0.000ns 2.825ns 1.254ns } { 0.000ns 0.292ns 0.738ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setu