{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clock3000000:inst3\|clkout Global clock " "Info: Automatically promoted signal \"clock3000000:inst3\|clkout\" to use Global clock" {  } { { "clock3000000.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/clock3000000.vhd" 7 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "Speakera:inst5\|PreCLK Global clock " "Info: Automatically promoted signal \"Speakera:inst5\|PreCLK\" to use Global clock" {  } { { "Speakera.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/Speakera.vhd" 10 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "ToneTaba:inst6\|Mux4~31 Global clock " "Info: Automatically promoted signal \"ToneTaba:inst6\|Mux4~31\" to use Global clock" {  } { { "ToneTaba.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/ToneTaba.vhd" 13 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clock2:inst2\|clkout Global clock " "Info: Automatically promoted some destinations of signal \"clock2:inst2\|clkout\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clock2:inst2\|clkout " "Info: Destination \"clock2:inst2\|clkout\" may be non-global or may not use global clock" {  } { { "clock2.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/clock2.vhd" 11 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "clock2.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/clock2.vhd" 11 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|CLR_SIGNAL Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|CLR_SIGNAL\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|CLR_SIGNAL~_wirecell " "Info: Destination \"sld_hub:sld_hub_inst\|CLR_SIGNAL~_wirecell\" may be non-global or may not use global clock" {  } { { "c:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/quartus/libraries/megafunctions/sld_hub.vhd" 316 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "c:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/quartus/libraries/megafunctions/sld_hub.vhd" 316 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\] " "Info: Destination \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\]\" may be non-global or may not use global clock" {  } { { "c:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/quartus/libraries/megafunctions/sld_hub.vhd" 1163 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " "Info: Destination \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]\" may be non-global or may not use global clock" {  } { { "c:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/quartus/libraries/megafunctions/sld_hub.vhd" 1163 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]~_wirecell " "Info: Destination \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]~_wirecell\" may be non-global or may not use global clock" {  } { { "c:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/quartus/libraries/megafunctions/sld_hub.vhd" 1163 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "c:/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/quartus/libraries/megafunctions/sld_hub.vhd" 1163 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.30 0 1 0 " "Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0 "" 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 3 19 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 3 total pin(s) used --  19 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 28 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 4 26 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  26 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 28 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.653 ns register register " "Info: Estimated most critical path is register to register delay of 6.653 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clock3000000:inst3\|count\[6\] 1 REG LAB_X12_Y8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X12_Y8; Fanout = 4; REG Node = 'clock3000000:inst3\|count\[6\]'" {  } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock3000000:inst3|count[6] } "NODE_NAME" } } { "clock3000000.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/clock3000000.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.192 ns) + CELL(0.575 ns) 1.767 ns clock3000000:inst3\|Add0~402COUT1 2 COMB LAB_X11_Y7 2 " "Info: 2: + IC(1.192 ns) + CELL(0.575 ns) = 1.767 ns; Loc. = LAB_X11_Y7; Fanout = 2; COMB Node = 'clock3000000:inst3\|Add0~402COUT1'" {  } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "1.767 ns" { clock3000000:inst3|count[6] clock3000000:inst3|Add0~402COUT1 } "NODE_NAME" } } { "clock3000000.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/clock3000000.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.847 ns clock3000000:inst3\|Add0~398COUT1 3 COMB LAB_X11_Y7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.847 ns; Loc. = LAB_X11_Y7; Fanout = 2; COMB Node = 'clock3000000:inst3\|Add0~398COUT1'" {  } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { clock3000000:inst3|Add0~402COUT1 clock3000000:inst3|Add0~398COUT1 } "NODE_NAME" } } { "clock3000000.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/clock3000000.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.927 ns clock3000000:inst3\|Add0~396COUT1 4 COMB LAB_X11_Y7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.927 ns; Loc. = LAB_X11_Y7; Fanout = 2; COMB Node = 'clock3000000:inst3\|Add0~396COUT1'" {  } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { clock3000000:inst3|Add0~398COUT1 clock3000000:inst3|Add0~396COUT1 } "NODE_NAME" } } { "clock3000000.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/clock3000000.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 2.007 ns clock3000000:inst3\|Add0~394COUT1 5 COMB LAB_X11_Y7 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 2.007 ns; Loc. = LAB_X11_Y7; Fanout = 2; COMB Node = 'clock3000000:inst3\|Add0~394COUT1'" {  } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { clock3000000:inst3|Add0~396COUT1 clock3000000:inst3|Add0~394COUT1 } "NODE_NAME" } } { "clock3000000.vhd" "" { Text "D:/Documents and Settings/yyy/桌面/yue/clock3000000.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 2.265 ns clock3000000:inst3\|Add0~388 6 COMB LAB_X11_Y7 6 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 2.265 ns; Loc. = LAB_X11_Y7; Fanout = 6; COMB Node = 'clock3000000:inst3\|Add0~388'" {  } { { "c:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus/bin/TimingCl