|Block1
spk <= Speakera:inst5.SpkS
inclk => kkk:inst.inclk0


|Block1|Speakera:inst5
clk => \DivideCLK:Count4[4].CLK
clk => \DivideCLK:Count4[3].CLK
clk => \DivideCLK:Count4[2].CLK
clk => \DivideCLK:Count4[1].CLK
clk => \DivideCLK:Count4[0].CLK
clk => PreCLK.CLK
Tone[0] => Count11~10.DATAB
Tone[1] => Count11~9.DATAB
Tone[2] => Count11~8.DATAB
Tone[3] => Count11~7.DATAB
Tone[4] => Count11~6.DATAB
Tone[5] => Count11~5.DATAB
Tone[6] => Count11~4.DATAB
Tone[7] => Count11~3.DATAB
Tone[8] => Count11~2.DATAB
Tone[9] => Count11~1.DATAB
Tone[10] => Count11~0.DATAB
SpkS <= SpkS~reg0.DB_MAX_OUTPUT_PORT_TYPE


|Block1|clock2:inst2
clkin => clkout~reg0.CLK
clkout <= clkout~reg0.DB_MAX_OUTPUT_PORT_TYPE


|Block1|kkk:inst
inclk0 => altpll:altpll_component.inclk[0]
c0 <= altpll:altpll_component.clk[0]


|Block1|kkk:inst|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => ~NO_FANOUT~
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
fbmimicbidir <= <GND>
clk[0] <= clk[0]~0.DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= <GND>
clk[2] <= <GND>
clk[3] <= <GND>
clk[4] <= <GND>
clk[5] <= <GND>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>


|Block1|ToneTaba:inst6
Index[0] => Mux17.IN19
Index[0] => Mux16.IN19
Index[0] => Mux15.IN19
Index[0] => Mux14.IN19
Index[0] => Mux13.IN19
Index[0] => Mux12.IN19
Index[0] => Mux11.IN19
Index[0] => Mux10.IN19
Index[0] => Mux9.IN19
Index[0] => Mux8.IN19
Index[0] => Mux7.IN19
Index[0] => Mux6.IN19
Index[0] => Mux5.IN19
Index[0] => Mux4.IN19
Index[0] => Mux3.IN19
Index[0] => Mux2.IN19
Index[0] => Mux1.IN19
Index[0] => Mux0.IN19
Index[1] => Mux17.IN18
Index[1] => Mux16.IN18
Index[1] => Mux15.IN18
Index[1] => Mux14.IN18
Index[1] => Mux13.IN18
Index[1] => Mux12.IN18
Index[1] => Mux11.IN18
Index[1] => Mux10.IN18
Index[1] => Mux9.IN18
Index[1] => Mux8.IN18
Index[1] => Mux7.IN18
Index[1] => Mux6.IN18
Index[1] => Mux5.IN18
Index[1] => Mux4.IN18
Index[1] => Mux3.IN18
Index[1] => Mux2.IN18
Index[1] => Mux1.IN18
Index[1] => Mux0.IN18
Index[2] => Mux17.IN17
Index[2] => Mux16.IN17
Index[2] => Mux15.IN17
Index[2] => Mux14.IN17
Index[2] => Mux13.IN17
Index[2] => Mux12.IN17
Index[2] => Mux11.IN17
Index[2] => Mux10.IN17
Index[2] => Mux9.IN17
Index[2] => Mux8.IN17
Index[2] => Mux7.IN17
Index[2] => Mux6.IN17
Index[2] => Mux5.IN17
Index[2] => Mux4.IN17
Index[2] => Mux3.IN17
Index[2] => Mux2.IN17
Index[2] => Mux1.IN17
Index[2] => Mux0.IN17
Index[3] => Mux17.IN16
Index[3] => Mux16.IN16
Index[3] => Mux15.IN16
Index[3] => Mux14.IN16
Index[3] => Mux13.IN16
Index[3] => Mux12.IN16
Index[3] => Mux11.IN16
Index[3] => Mux10.IN16
Index[3] => Mux9.IN16
Index[3] => Mux8.IN16
Index[3] => Mux7.IN16
Index[3] => Mux6.IN16
Index[3] => Mux5.IN16
Index[3] => Mux4.IN16
Index[3] => Mux3.IN16
Index[3] => Mux2.IN16
Index[3] => Mux1.IN16
Index[3] => Mux0.IN16
CODE[0] <= CODE[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
CODE[1] <= CODE[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
CODE[2] <= CODE[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
CODE[3] <= CODE[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
HIGH <= HIGH$latch.DB_MAX_OUTPUT_PORT_TYPE
Tone[0] <= Tone[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
Tone[1] <= Tone[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
Tone[2] <= Tone[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
Tone[3] <= Tone[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
Tone[4] <= Tone[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
Tone[5] <= Tone[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
Tone[6] <= Tone[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
Tone[7] <= Tone[7]$latch.DB_MAX_OUTPUT_PORT_TYPE
Tone[8] <= Tone[8]$latch.DB_MAX_OUTPUT_PORT_TYPE
Tone[9] <= Tone[9]$latch.DB_MAX_OUTPUT_PORT_TYPE
Tone[10] <= Tone[10]$latch.DB_MAX_OUTPUT_PORT_TYPE


|Block1|notetabs:inst4
clk => counter[7].CLK
clk => counter[6].CLK
clk => counter[5].CLK
clk => counter[4].CLK
clk => counter[3].CLK
clk => counter[2].CLK
clk => counter[1].CLK
clk => counter[0].CLK
clk => music_rom:u1.clock
toneindex[0] <= music_rom:u1.q[0]
toneindex[1] <= music_rom:u1.q[1]
toneindex[2] <= music_rom:u1.q[2]
toneindex[3] <= music_rom:u1.q[3]


|Block1|notetabs:inst4|music_rom:u1
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]


|Block1|notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_gq41:auto_generated.address_a[0]
address_a[1] => altsyncram_gq41:auto_generated.address_a[1]
address_a[2] => altsyncram_gq41:auto_generated.address_a[2]
address_a[3] => altsyncram_gq41:auto_generated.address_a[3]
address_a[4] => altsyncram_gq41:auto_generated.address_a[4]
address_a[5] => altsyncram_gq41:auto_generated.address_a[5]
address_a[6] => altsyncram_gq41:auto_generated.address_a[6]
address_a[7] => altsyncram_gq41:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_gq41:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_gq41:auto_generated.q_a[0]
q_a[1] <= altsyncram_gq41:auto_generated.q_a[1]
q_a[2] <= altsyncram_gq41:auto_generated.q_a[2]
q_a[3] <= altsyncram_gq41:auto_generated.q_a[3]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|Block1|notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated
address_a[0] => altsyncram_8962:altsyncram1.address_a[0]
address_a[1] => altsyncram_8962:altsyncram1.address_a[1]
address_a[2] => altsyncram_8962:altsyncram1.address_a[2]
address_a[3] => altsyncram_8962:altsyncram1.address_a[3]
address_a[4] => altsyncram_8962:altsyncram1.address_a[4]
address_a[5] => altsyncram_8962:altsyncram1.address_a[5]
address_a[6] => altsyncram_8962:altsyncram1.address_a[6]
address_a[7] => altsyncram_8962:altsyncram1.address_a[7]
clock0 => altsyncram_8962:altsyncram1.clock0
q_a[0] <= altsyncram_8962:altsyncram1.q_a[0]
q_a[1] <= altsyncram_8962:altsyncram1.q_a[1]
q_a[2] <= altsyncram_8962:altsyncram1.q_a[2]
q_a[3] <= altsyncram_8962:altsyncram1.q_a[3]


|Block1|notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|altsyncram_8962:altsyncram1
address_a[0] => ram_block3a0.PORTAADDR
address_a[0] => ram_block3a1.PORTAADDR
address_a[0] => ram_block3a2.PORTAADDR
address_a[0] => ram_block3a3.PORTAADDR
address_a[1] => ram_block3a0.PORTAADDR1
address_a[1] => ram_block3a1.PORTAADDR1
address_a[1] => ram_block3a2.PORTAADDR1
address_a[1] => ram_block3a3.PORTAADDR1
address_a[2] => ram_block3a0.PORTAADDR2
address_a[2] => ram_block3a1.PORTAADDR2
address_a[2] => ram_block3a2.PORTAADDR2
address_a[2] => ram_block3a3.PORTAADDR2
address_a[3] => ram_block3a0.PORTAADDR3
address_a[3] => ram_block3a1.PORTAADDR3
address_a[3] => ram_block3a2.PORTAADDR3
address_a[3] => ram_block3a3.PORTAADDR3
address_a[4] => ram_block3a0.PORTAADDR4
address_a[4] => ram_block3a1.PORTAADDR4
address_a[4] => ram_block3a2.PORTAADDR4
address_a[4] => ram_block3a3.PORTAADDR4
address_a[5] => ram_block3a0.PORTAADDR5
address_a[5] => ram_block3a1.PORTAADDR5
address_a[5] => ram_block3a2.PORTAADDR5
address_a[5] => ram_block3a3.PORTAADDR5
address_a[6] => ram_block3a0.PORTAADDR6
address_a[6] => ram_block3a1.PORTAADDR6