address_a[6] => ram_block3a2.PORTAADDR6
address_a[6] => ram_block3a3.PORTAADDR6
address_a[7] => ram_block3a0.PORTAADDR7
address_a[7] => ram_block3a1.PORTAADDR7
address_a[7] => ram_block3a2.PORTAADDR7
address_a[7] => ram_block3a3.PORTAADDR7
address_b[0] => ram_block3a0.PORTBADDR
address_b[0] => ram_block3a1.PORTBADDR
address_b[0] => ram_block3a2.PORTBADDR
address_b[0] => ram_block3a3.PORTBADDR
address_b[1] => ram_block3a0.PORTBADDR1
address_b[1] => ram_block3a1.PORTBADDR1
address_b[1] => ram_block3a2.PORTBADDR1
address_b[1] => ram_block3a3.PORTBADDR1
address_b[2] => ram_block3a0.PORTBADDR2
address_b[2] => ram_block3a1.PORTBADDR2
address_b[2] => ram_block3a2.PORTBADDR2
address_b[2] => ram_block3a3.PORTBADDR2
address_b[3] => ram_block3a0.PORTBADDR3
address_b[3] => ram_block3a1.PORTBADDR3
address_b[3] => ram_block3a2.PORTBADDR3
address_b[3] => ram_block3a3.PORTBADDR3
address_b[4] => ram_block3a0.PORTBADDR4
address_b[4] => ram_block3a1.PORTBADDR4
address_b[4] => ram_block3a2.PORTBADDR4
address_b[4] => ram_block3a3.PORTBADDR4
address_b[5] => ram_block3a0.PORTBADDR5
address_b[5] => ram_block3a1.PORTBADDR5
address_b[5] => ram_block3a2.PORTBADDR5
address_b[5] => ram_block3a3.PORTBADDR5
address_b[6] => ram_block3a0.PORTBADDR6
address_b[6] => ram_block3a1.PORTBADDR6
address_b[6] => ram_block3a2.PORTBADDR6
address_b[6] => ram_block3a3.PORTBADDR6
address_b[7] => ram_block3a0.PORTBADDR7
address_b[7] => ram_block3a1.PORTBADDR7
address_b[7] => ram_block3a2.PORTBADDR7
address_b[7] => ram_block3a3.PORTBADDR7
clock0 => ram_block3a0.CLK0
clock0 => ram_block3a1.CLK0
clock0 => ram_block3a2.CLK0
clock0 => ram_block3a3.CLK0
clock1 => ram_block3a0.CLK1
clock1 => ram_block3a1.CLK1
clock1 => ram_block3a2.CLK1
clock1 => ram_block3a3.CLK1
data_b[0] => ram_block3a0.PORTBDATAIN
data_b[1] => ram_block3a1.PORTBDATAIN
data_b[2] => ram_block3a2.PORTBDATAIN
data_b[3] => ram_block3a3.PORTBDATAIN
q_a[0] <= ram_block3a0.PORTADATAOUT
q_a[1] <= ram_block3a1.PORTADATAOUT
q_a[2] <= ram_block3a2.PORTADATAOUT
q_a[3] <= ram_block3a3.PORTADATAOUT
q_b[0] <= ram_block3a0.PORTBDATAOUT
q_b[1] <= ram_block3a1.PORTBDATAOUT
q_b[2] <= ram_block3a2.PORTBDATAOUT
q_b[3] <= ram_block3a3.PORTBDATAOUT
wren_b => ram_block3a0.PORTBRE
wren_b => ram_block3a1.PORTBRE
wren_b => ram_block3a2.PORTBRE
wren_b => ram_block3a3.PORTBRE


|Block1|notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|sld_mod_ram_rom:mgl_prim2
tck_usr <= raw_tck.DB_MAX_OUTPUT_PORT_TYPE
address[0] <= ram_rom_addr_reg[0].DB_MAX_OUTPUT_PORT_TYPE
address[1] <= ram_rom_addr_reg[1].DB_MAX_OUTPUT_PORT_TYPE
address[2] <= ram_rom_addr_reg[2].DB_MAX_OUTPUT_PORT_TYPE
address[3] <= ram_rom_addr_reg[3].DB_MAX_OUTPUT_PORT_TYPE
address[4] <= ram_rom_addr_reg[4].DB_MAX_OUTPUT_PORT_TYPE
address[5] <= ram_rom_addr_reg[5].DB_MAX_OUTPUT_PORT_TYPE
address[6] <= ram_rom_addr_reg[6].DB_MAX_OUTPUT_PORT_TYPE
address[7] <= ram_rom_addr_reg[7].DB_MAX_OUTPUT_PORT_TYPE
enable_write <= enable_write~0.DB_MAX_OUTPUT_PORT_TYPE
data_write[0] <= ram_rom_data_reg[0].DB_MAX_OUTPUT_PORT_TYPE
data_write[1] <= ram_rom_data_reg[1].DB_MAX_OUTPUT_PORT_TYPE
data_write[2] <= ram_rom_data_reg[2].DB_MAX_OUTPUT_PORT_TYPE
data_write[3] <= ram_rom_data_reg[3].DB_MAX_OUTPUT_PORT_TYPE
data_read[0] => ram_rom_data_reg~7.DATAB
data_read[1] => ram_rom_data_reg~6.DATAB
data_read[2] => ram_rom_data_reg~5.DATAB
data_read[3] => ram_rom_data_reg~4.DATAB
raw_tck => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.TCK
raw_tck => ram_rom_addr_reg[7].CLK
raw_tck => ram_rom_addr_reg[6].CLK
raw_tck => ram_rom_addr_reg[5].CLK
raw_tck => ram_rom_addr_reg[4].CLK
raw_tck => ram_rom_addr_reg[3].CLK
raw_tck => ram_rom_addr_reg[2].CLK
raw_tck => ram_rom_addr_reg[1].CLK
raw_tck => ram_rom_addr_reg[0].CLK
raw_tck => ram_rom_data_reg[3].CLK
raw_tck => ram_rom_data_reg[2].CLK
raw_tck => ram_rom_data_reg[1].CLK
raw_tck => ram_rom_data_reg[0].CLK
raw_tck => ram_rom_data_shift_cntr_reg[2].CLK
raw_tck => ram_rom_data_shift_cntr_reg[1].CLK
raw_tck => ram_rom_data_shift_cntr_reg[0].CLK
raw_tck => ir_loaded_address_reg[3].CLK
raw_tck => ir_loaded_address_reg[2].CLK
raw_tck => ir_loaded_address_reg[1].CLK
raw_tck => ir_loaded_address_reg[0].CLK
raw_tck => bypass_reg_out.CLK
raw_tck => is_in_use_reg.CLK
raw_tck => tck_usr.DATAIN
tdi => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.TDI
tdi => ram_rom_data_reg~0.DATAB
tdi => ram_rom_addr_reg~8.DATAB
tdi => bypass_reg_out.DATAIN
usr1 => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.USR1
usr1 => name_gen~0.IN1
usr1 => dr_scan.IN1
jtag_state_cdr => name_gen~1.IN1
jtag_state_sdr => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.SHIFT
jtag_state_sdr => name_gen~1.IN0
jtag_state_sdr => sdr.IN1
jtag_state_e1dr => ram_rom_update_write_ena.IN1
jtag_state_udr => sld_rom_sr:ram_rom_logic_gen:name_gen:info_rom_sr.UPDATE
jtag_state_udr => udr.IN0
jtag_state_uir => ~NO_FANOUT~
clrn => bypass_reg_out.ACLR
clrn => is_in_use_reg.ACLR
ena => name_gen~0.IN0
ena => dr_scan.IN0
ena => bypass_reg_out.ENA
ir_in[0] => ram_rom_addr_reg[7].ACLR
ir_in[0] => ram_rom_addr_reg[6].ACLR
ir_in[0] => ram_rom_addr_reg[5].ACLR
ir_in[0] => ram_rom_addr_reg[4].ACLR
ir_in[0] => ram_rom_addr_reg[3].ACLR
ir_in[0] => ram_rom_addr_reg[2].ACLR
ir_in[0] => ram_rom_addr_reg[1].ACLR
ir_in[0] => ram_rom_addr_reg[0].ACLR
ir_in[0] => is_in_use_reg~1.OUTPUTSELECT
ir_in[0] => tdo~1.OUTPUTSELECT
ir_in[0] => process4~0.IN0
ir_in[1] => ram_rom_incr_addr~0.IN0
ir_in[1] => process1~2.IN0
ir_in[1] => process1~0.IN0
ir_in[2] => enable_write~0.IN0
ir_in[2] => ram_rom_incr_addr~1.IN0
ir_in[2] => process1~2.IN1
ir_in[3] => ram_rom_data_shift_cntr_reg[2].ACLR
ir_in[3] => ram_rom_data_shift_cntr_reg[1].ACLR
ir_in[3] => ram_rom_data_shift_cntr_reg[0].ACLR
ir_in[3] => process4~1.IN0
ir_in[3] => process1~1.IN0
ir_in[3] => process0~0.IN1
ir_in[4] => is_in_use_reg~0.OUTPUTSELECT
ir_in[4] => process4~0.IN1
ir_out[0] <= is_in_use_reg.DB_MAX_OUTPUT_PORT_TYPE
ir_out[1] <= ir_loaded_address_reg[0].DB_MAX_OUTPUT_PORT_TYPE
ir_out[2] <= ir_loaded_address_reg[1].DB_MAX_OUTPUT_PORT_TYPE
ir_out[3] <= ir_loaded_address_reg[2].DB_MAX_OUTPUT_PORT_TYPE
ir_out[4] <= ir_loaded_address_reg[3].DB_MAX_OUTPUT_PORT_TYPE
tdo <= tdo~1.DB_MAX_OUTPUT_PORT_TYPE


|Block1|notetabs:inst4|music_rom:u1|altsyncram:altsyncram_component|altsyncram_gq41:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
ROM_DATA[0] => Mux3.IN131
ROM_DATA[1] => Mux2.IN131
ROM_DATA[2] => Mux1.IN131
ROM_DATA[3] => Mux0.IN131
ROM_DATA[4] => Mux3.IN127
ROM_DATA[5] => Mux2.IN127
ROM_DATA[6] => Mux1.IN127
ROM_DATA[7] => Mux0.IN127
ROM_DATA[8] => Mux3.IN123
ROM_DATA[9] => Mux2.IN123
ROM_DATA[10] => Mux1.IN123
ROM_DATA[11] => Mux0.IN123
ROM_DATA[12] => Mux3.IN119
ROM_DATA[13] => Mux2.IN119
ROM_DATA[14] => Mux1.IN119
ROM_DATA[15] => Mux0.IN119
ROM_DATA[16] => Mux3.IN115
ROM_DATA[17] => Mux2.IN115
ROM_DATA[18] => Mux1.IN115
ROM_DATA[19] => Mux0.IN115
ROM_DATA[20] => Mux3.IN111
ROM_DATA[21] => Mux2.IN111
ROM_DATA[22] => Mux1.IN111
ROM_DATA[23] => Mux0.IN111
ROM_DATA[24] => Mux3.IN107
ROM_DATA[25] => Mux2.IN107
ROM_DATA[26] => Mux1.IN107
ROM_DATA[27] => Mux0.IN107
ROM_DATA[28] => Mux3.IN103
ROM_DATA[29] => Mux2.IN103
ROM_DATA[30] => Mux1.IN103
ROM_DATA[31] => Mux0.IN103
ROM_DATA[32] => Mux3.IN99
ROM_DATA[33] => Mux2.IN99
ROM_DATA[34] => Mux1.IN99
ROM_DATA[35] => Mux0.IN99
ROM_DATA[36] => Mux3.IN95
ROM_DATA[37] => Mux2.IN95
ROM_DATA[38] => Mux1.IN95
ROM_DATA[39] => Mux0.IN95
ROM_DATA[40] => Mux3.IN91
ROM_DATA[41] => Mux2.IN91
ROM_DATA[42] => Mux1.IN91
ROM_DATA[43] => Mux0.IN91
ROM_DATA[44] => Mux3.IN87
ROM_DATA[45] => Mux2.IN87
ROM_DATA[46] => Mux1.IN87
ROM_DATA[47] => Mux0.IN87
ROM_DATA[48] => Mux3.IN83
ROM_DATA[49] => Mux2.IN83
ROM_DATA[50] => Mux1.IN83
ROM_DATA[51] => Mux0.IN83
ROM_DATA[52] => Mux3.IN79
ROM_DATA[53] => Mux2.IN79
ROM_DATA[54] => Mux1.IN79
ROM_DATA[55] => Mux0.IN79
ROM_DATA[56] => Mux3.IN75
ROM_DATA[57] => Mux2.IN75
ROM_DATA[58] => Mux1.IN75
ROM_DATA[59] => Mux0.IN75
ROM_DATA[60] => Mux3.IN71
ROM_DATA[61] => Mux2.IN71
ROM_DATA[62] => Mux1.IN71
ROM_DATA[63] => Mux0.IN71
ROM_DATA[64] => Mux3.IN67
ROM_DATA[65] => Mux2.IN67
ROM_DATA[66] => Mux1.IN67
ROM_DATA[67] => Mux0.IN67
ROM_DATA[68] => Mux3.IN63
ROM_DATA[69] => Mux2.IN63
ROM_DATA[70] => Mux1.IN63
ROM_DATA[71] => Mux0.IN63
ROM_DATA[72] => Mux3.IN59
ROM_DATA[73] => Mux2.IN59
ROM_DATA[74] => Mux1.IN59
ROM_DATA[75] => Mux0.IN59
ROM_DATA[76] => Mux3.IN55
ROM_DATA[77] => Mux2.IN55
ROM_DATA[78] => Mux1.IN55
ROM_DATA[79] => Mux0.IN55
TCK => word_counter[4].CLK
TCK => word_counter[3].CLK
TCK => word_counter[2].CLK
TCK => word_counter[1].CLK
TCK => word_counter[0].CLK
TCK => WORD_SR[3].CLK
TCK => WORD_SR[2].CLK
TCK => WORD_SR[1].CLK
TCK => WORD_SR[0].CLK
SHIFT => WORD_SR~3.OUTPUTSELECT
SHIFT => WORD_SR~2.OUTPUTSELECT
SHIFT => WORD_SR~1.OUTPUTSELECT
SHIFT => WORD_SR~0.OUTPUTSELECT
SHIFT => word_counter~9.OUTPUTSELECT
SHIFT => word_counter~8.OUTPUTSELECT
SHIFT => word_counter~7.OUTPUTSELECT
SHIFT => word_counter~6.OUTPUTSELECT
SHIFT => word_counter~5.OUTPUTSELECT
UPDATE => clear_signal.IN0
USR1 => clear_signal.IN1
ENA => WORD_SR~7.OUTPUTSELECT
ENA => WORD_SR~6.OUTPUTSELECT
ENA => WORD_SR~5.OUTPUTSELECT
ENA => WORD_SR~4.OUTPUTSELECT
ENA => word_counter~14.OUTPUTSELECT
ENA => word_counter~13.OUTPUTSELECT
ENA => word_counter~12.OUTPUTSELECT
ENA => word_counter~11.OUTPUTSELECT
ENA => word_counter~10.OUTPUTSELECT
TDI => WORD_SR~0.DATAA
TDO <= WORD_SR[0].DB_MAX_OUTPUT_PORT_TYPE


|Block1|clock3000000:inst3
clkin => count[21].CLK
clkin => count[20].CLK
clkin => count[19].CLK
clkin => count[18].CLK
clkin => count[17].CLK
clkin => count[16].CLK
clkin => count[15].CLK
clkin => count[14].CLK
clkin => count[13].CLK
clkin => count[12].CLK
clkin => count[11].CLK
clkin => count[10].CLK
clkin => count[9].CLK
clkin => count[8].CLK
clkin => count[7].CLK
clkin => count[6].CLK
clkin => count[5].CLK
clkin => count[4].CLK
clkin => count[3].CLK
clkin => count[2].CLK
clkin => count[1].CLK
clkin => count[0].CLK
clkin => clkout~reg0.CLK
clkout <= clkout~reg0.DB_MAX_OUTPUT_PORT_TYPE