#pragma NOIV               // Do not generate interrupt vectors

//-----------------------------------------------------------------------------
// File:     periph.c
// Contents: Hooks required to implement USB peripheral function.
//
// Format:   indent 3.  NO TABS!
//
//--------------------------------------------------------------------------
// $Archive: /USB/atapifx2/NX2LP/SRC/CY3686FW/periph.c $
// $Modtime: 8/08/05 10:01a $
// $Revision: 1 $
//--------------------------------------------------------------------------
//
// Copyright 2005, Cypress Semiconductor Corporation.
//
// This software is owned by Cypress Semiconductor Corporation (Cypress)
// and is protected by and subject to worldwide patent protection (United
// States and foreign), United States copyright laws and international 
// treaty provisions. Cypress hereby grants to licensee a personal, 
// non-exclusive, non-transferable license to copy, use, modify, create 
// derivative works of, and compile the Cypress Source Code and derivative 
// works for the sole purpose of creating custom software in support of 
// licensee product to be used only in conjunction with a Cypress integrated 
// circuit as specified in the applicable agreement. Any reproduction, 
// modification, translation, compilation, or representation of this 
// software except as specified above is prohibited without the express 
// written permission of Cypress.
//
// Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND,EXPRESS OR IMPLIED, 
// WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
// Cypress reserves the right to make changes without further notice to the
// materials described herein. Cypress does not assume any liability arising
// out of the application or use of any product or circuit described herein.
// Cypress does not authorize its products for use as critical components in
// life-support systems where a malfunction or failure may reasonably be
// expected to result in significant injury to the user. The inclusion of
// Cypress' product in a life-support systems application implies that the
// manufacturer assumes all risk of such use and in doing so indemnifies
// Cypress against all charges.
//
// Use may be limited by and subject to the applicable Cypress software
// license agreement.
//
//--------------------------------------------------------------------------
#include "globals.h"


//-----------------------------------------------------------------------------
// Hardware/Software Initialization will be done here
// Search for USER_INIT and modify the IOD, OED, OEA for addition HW 
// Modification
//-----------------------------------------------------------------------------
void TD_Init(void)             // Called once at startup
{
   MPAGE     = 0xe6;              // Map to Hardware register page 0xE600

   IFCONFIG = IFCONFIG_DEFAULT;
   CPUCS = 0x14;            // set clock to 48MHz.     

   // Enable both autoptrs. ONLY use AUTOPTR2 for writing small amounts of data 
   AUTOPTRSETUP = 0x7;
   AUTOPTRH2 = MSB(EP4FIFOBUF);

   IT0 = 0;                 // Make Interrupt 0 level triggered
   FLOWSTATE = 0x00;        // turn off flowstate 
   FIFOPINPOLAR = 0x00;     // ff pin is active low
   PINFLAGSAB = 0x00;       // FLAGA PF for FIFO selected by FIFOADR[1..0]
   PINFLAGSCD = 0x00;       // FLAGB FF for FIFO selected by FIFOADR[1..0]

   // GPIF and CTL configuration
   GPIFCTLCFG = 0x0;        // 
   GPIFIDLECS = 0;          // tristate data bus during idle interval
   EP2FIFOCFG = 0x00;       // byte wide
   EP6FIFOCFG = 0x00;       // byte wide
   EP8FIFOCFG = 0x00;       // byte wide
   EP2FIFOPFH = 0x00;       // PF=0 when BC > PF -> Decis=0 (1 byte in FIFO)
   EP2FIFOPFL = 0x00;       // PF and BC refer to the current pkt -> PKTSTAT=0
   EP2GPIFPFSTOP = 0;       // Do not stop on PF
   EP6GPIFFLGSEL = 0x01;
   EP2GPIFFLGSEL = 0x01;    //  Empty for the EP2

   // Single write is 3, Single read is 2, write is 1, Read is waveform 0 
   GPIFWFSELECT = 0xe4;
   GPIFREADYCFG = 0x20;     // RDY5 is the transaction count expired
   GPIFIDLECTL  = 0x7;      // x111x111 - CTL3 not enabled  
                            // ||||||||_CTL0 = 1 during idle
                            // |||||||__CTL1 = 1 during idle
                            // ||||||___CTL2 = 1 during idle
                            // ||||_____CTL0 output enable
                            // |||______CTL1 output enable
                            // ||_______CTL2 output enable

   // Endpoint initialization
   EP2CFG = EP2CFG_DEFAULT;
   EP4CFG = EP4CFG_DEFAULT;

   EP4FIFOCFG = EP4FIFOCFG_DEFAULT; // Setup EP4 FIFO CFG
   EP4GPIFFLGSEL = 0x02;            // GPIF will use the full flag as the fifoflag

   // mark all unused endpoints invalid - setting each reg to 0x22 instead of just clearing
   // the valid bit to save code space.  0x22 basically sets all of these endpoints to 
   // not valid, bulk, double 512 buffered.
#ifdef HID
   EP1INCFG = 0xb0;                      // Setup EP1 IN
#else
   EP1INCFG = 
#endif
   EP1OUTCFG = EP8CFG = EP6CFG = 0x22;
   P_EP6CFG = EP6CFG_IN_DEFAULT;         // Use from inand.h
   REVCTL = bmNOAUTOARM | bmSKIPCOMMIT;  // Enable enhanced packet handling.  
                                         // requires us to use OUTPKTEND to arm OUT endpoint
   // init state/reset variables
   currentState = UNCONFIGURED;
   phaseErrorState = 0;
   CKCON = 0x10;              // Zero wait state
   LED0_OFF();                // turn off both LEDs
   LED1_OFF();
   P_ECCCFG = 0x00;           // set the NAND ECC calculator to 256 byte mode

   GPIFABORT = 0xff;              // force GPIF goto idle
   P_EP6BCH = 0xff;           // default

   // USER_INIT:  
   //   - Default PortD: set all pins = output
   //   - Default PortE: set all pins = output, except pin 5.
   //   - 512 NAND FW: Only 2 NAND chip selects on PortD (PD0 and PD1)
   //   - 2K  NAND FW:  Support PD0-PD3
   
   OED = 0xFF;                // NAND chip select use PD0-7
   IOD = 0xFF;
   OEA = 0xDF;                // 1101 1111 -- PA5 (WP switch) is an input

   // relocate descriptor data to halfKBuffer when we know it's the first time
   // i.e. On POR, TR0=0 = firsttime
   if (!TR0)
   {        
      memset16(halfKBuffer+cHALF_BUFF_OFFSET, 0, (cNAND_CFG_LENGTH/16));   // clear all zeros
      mymemmovexx(halfKBuffer, (char xdata *) &DeviceDscr, (WORD)&DscrEndOffset);
      mymemmovexx(&GPIF_WAVE_DATA, (BYTE xdata *) WaveDataPioUDMA, 128);   // load wave forms in memory
      InitNAND();  // Only call this when POR
   }
   // reset the EP4 FIFO.  If we are here as the result of a USB reset or MSC
   // Reset Recovery, EP4 may need to be cleaned up.
   P_FIFORESET = 0x04;
   // arm the OUT endpoint.  By default OUT endpoints come up unarmed.
   ResetAndArmEp2();
}
//-----------------------------------------------------------------------------
// Task Dispatcher hooks:
//     The following hooks are called by the task dispatcher.
//     USB Mass storage Command Processing here
//-----------------------------------------------------------------------------
void TD_Poll(void)             // Called repeatedly while the device is idle
{
    BYTE cmd;
    // check EP2 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty
    if((P_EP2CS & bmEPEMPTY)) return;

    currentState = WAIT_FOR_CBW;
    AUTOPTR1H = MSB(EP2FIFOBUF); 
    AUTOPTR1L = LSB(EP2FIFOBUF); 

    if ((P_XAUTODAT1 != 'U' ||   // Check for "USBC"
         P_XAUTODAT1 != 'S' ||
         P_XAUTODAT1 != 'B' ||
         P_XAUTODAT1 != 'C')|| (EP2BC != 31)
        )
    {
         P_EP2CS = P_EP4CS = bmEPSTALL;
         phaseErrorState = 1;
         return;
    }

    LED0_ON();
    *(((BYTE *) &cbwTagLow)+0) = P_XAUTODAT1;
    *(((BYTE *) &cbwTagLow)+1) = P_XAUTODAT1;
    *(((BYTE *) &cbwTagHi)+0)  = P_XAUTODAT1;
    *(((BYTE *) &cbwTagHi)+1)  = P_XAUTODAT1;

    // Get the length (convert from little endian)
    *(((BYTE *) &dataTransferLen)+3) = P_XAUTODAT1; 
    *(((BYTE *) &dataTransferLen)+2) = P_XAUTODAT1;  // "Residue"
    *(((BYTE *) &dataTransferLen)+1) = P_XAUTODAT1;  // "Residue"
    *(((BYTE *) &dataTransferLen)+0) = P_XAUTODAT1;  // "Residue"

   directionIn = P_XAUTODAT1 & 0x80;
#ifdef USE_2LUN
   bLUN1       = P_XAUTODAT1;                        // extract LUN
#endif
   AUTOPTR1L = LSB(EP2FIFOBUF+CBW_DATA_START+2); 
   ((BYTE *) &gNextLBA)[0] = P_XAUTODAT1;
   ((BYTE *) &gNextLBA)[1] = P_XAUTODAT1;
   ((BYTE *) &gNextLBA)[2] = P_XAUTODAT1;
   ((BYTE *) &gNextLBA)[3] = P_XAUTODAT1;
   P_XAUTODAT1;
   ((BYTE *) &gSectorcount)[0] = P_XAUTODAT1;
   ((BYTE *) &gSectorcount)[1] = P_XAUTODAT1;
   bErr = 0;
   cmd = EP2FIFOBUF[0xf];
   if (gPartialCpy)
   {
      // if the current command is not a write to our expected LBA
      // then complete the partial block write
      if (!((cmd == WRITE_10) && (dwLBA == gNextLBA)))
      {
         NAND_PCPY(gPartialCpy, xLBA3);
         gPartialCpy = 0;  // Reset partial cpy
         nEraseBlock();
         DISABLE_NAND();
      }

   }

#ifdef USE_2LUN
   if (bLUN1)
      gNextLBA += (gDriveCapacity+1);  // adjust for next block
#endif

   dwLBA = gNextLBA;

   switch(cmd)
   {
      //    -- Read that starts after the end of the disk
      //    -- Read that starts inside the disk and continues beyond the end of the disk
      //    -- Unrecoverable ECC error
      // case READ_06:
      case READ_10:
         // Add support for BOT test
         cmd = xFerLen2>>1; 
         if (xFerLen1&1) cmd |= 0x80; 
         if ((cmd != xSector)  || bEject || !directionIn)
         {
            failedIn();
            cmd = USBS_FAILED;
            break;
         }
         nReadPages();
         cmd = ChkErr();
         break;
      //case WRITE_06:
      case WRITE_10:
      case WRITE_AND_VERIFY_10:
         P_OUTPKTEND = 0x82;
         // This check doesn't seem to be required by Windows.  They will read and obey the WP
         // state reported in the mode_sense data.  This code is here for SCSI passthrough-enabled