?? register.h
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#ifndef _REGISTER_H
#define _REGISTER_H
#include "defBF535.h"
#define PVUL volatile unsigned long *
#define PVUS volatile unsigned short *
#define PVUB volatile unsigned char *
// NOTE: CHIPID is defined to the wrong value in <def21535.h> use chipId
// instead
#define chipId 0xFFC048C0 // Chip ID Register
/************************************************************************************
System MMR Register
*************************************************************************************/
/*==================================================================================
L2 MISR MMRs (0xFFC0 0000-0xFFC0 03FF)
====================================================================================*/
#define MISR_CTL_REG (*(PVUL)(MISR_CTL)) // Control Register
#define MISR_RMISR0_REG (*(PVUL)(MISR_RMISR0)) // coreL2[31:0] read bus
#define MISR_RMISR1_REG (*(PVUL)(MISR_RMISR1)) // coreL2[63:32] read bus
#define MISR_RMISR2_REG (*(PVUL)(MISR_RMISR2)) // sysL2[31:0] read bus
#define MISR_WMISR0_REG (*(PVUL)(MISR_WMISR0)) // coreL2[31:0] write bus
#define MISR_WMISR1_REG (*(PVUL)(MISR_WMISR1)) // coreL2[63:32] write bus
#define MISR_WMISR2_REG (*(PVUL)(MISR_WMISR2)) // sysL2[31:0] write bus
/*==================================================================================
// Clock and System Control (0xFFC0 0400-0xFFC0 07FF)
====================================================================================*/
#define PLLCTL_REG (*(PVUL)(PLLCTL)) // PLL Control register (32-bit)
#define PLLSTAT_REG (*(PVUS)(PLLSTAT)) // PLL Status register
#define LOCKCNT_REG (*(PVUS)(LOCKCNT)) // PLL Lock Counter register
#define IOCKR_REG (*(PVUS)(IOCKR)) // Peripheral Clock Enable register (32-bit)
#define SWRST_REG (*(PVUL)(SWRST)) // Software Reset Register
#define SYSCR_REG (*(PVUS)(SYSCR)) // System Configuration register (RCSR)
/*==================================================================================
// JTAG/Debug Communication Channel (0xFFC0 0800-0xFFC0 0BFF)
====================================================================================*/
#define CHIPID_REG (*(PVUL)(CHIPID)) // Device ID Register
#define chipId_REG (*(PVUL)(chipId)) // Device ID Register
/*==================================================================================
// System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF)
====================================================================================*/
#define SIC_RVECT_REG (*(PVUL)(SIC_RVECT)) // Reset Vector Register
#define SIC_IAR0_REG (*(PVUL)(SIC_IAR0)) // Interrupt Assignment Register 0
#define SIC_IAR1_REG (*(PVUL)(SIC_IAR1)) // Interrupt Assignment Register 1
#define SIC_IAR2_REG (*(PVUL)(SIC_IAR2)) // Interrupt Assignment Register 2
#define SIC_IMASK_REG (*(PVUL)(SIC_IMASK)) // Interrupt Mask Register
#define SIC_ISR_REG (*(PVUL)(SIC_ISR)) // Interrupt Status Register
#define SIC_IWR_REG (*(PVUL)(SIC_IWR)) // Interrupt Wakeup Register
/*==================================================================================
// Watchdog Timer (0xFFC0 1000-0xFFC0 13FF)
====================================================================================*/
#define WDOGCTL_REG (*(PVUL)(WDOGCTL)) // Watchdog Control Register
#define WDOGCNT_REG (*(PVUL)(WDOGCNT)) // Watchdog Count Register
#define WDOGSTAT_REG (*(PVUL)(WDOGSTAT)) // Watchdog Status Register
/*==================================================================================
// Real Time Clock (0xFFC0 1400-0xFFC0 17FF)
====================================================================================*/
#define RTCSTAT_REG (*(PVUL)(RTCSTAT)) // RTC Status Register
#define RTCICTL_REG (*(PVUL)(RTCICTL)) // RTC Interrupt Control Register
#define RTCISTAT_REG (*(PVUL)(RTCISTAT)) // RTC Interrupt Status Register
#define RTCSWCNT_REG (*(PVUL)(RTCSWCNT)) // RTC Stopwatch Count Register
#define RTCALARM_REG (*(PVUL)(RTCALARM)) // RTC Alarm Time Register
#define RTCFAST_REG (*(PVUL)(RTCFAST)) // RTC Prescaler Control Register
/*==================================================================================
// UART 0 Controller (0xFFC0 1800-0xFFC0 1BFF)
====================================================================================*/
#define UART0_THR_REG (*(PVUB)(UART0_THR)) // Transmit Holding register
#define UART0_RBR_REG (*(PVUB)(UART0_RBR)) // Receive Buffer register
#define UART0_DLL_REG (*(PVUB)(UART0_DLL)) // Divisor Latch (Low-Byte)
#define UART0_IER_REG (*(PVUB)(UART0_IER)) // Interrupt Enable Register
#define UART0_DLH_REG (*(PVUB)(UART0_DLH)) // Divisor Latch (High-Byte)
#define UART0_IIR_REG (*(PVUB)(UART0_IIR)) // Interrupt Identification Register
#define UART0_LCR_REG (*(PVUB)(UART0_LCR)) // Line Control Register
#define UART0_MCR_REG (*(PVUB)(UART0_MCR)) // Module Control Register
#define UART0_LSR_REG (*(PVUB)(UART0_LSR)) // Line Status Register
#define UART0_MSR_REG (*(PVUB)(UART0_MSR)) // MSR Modem Status Register
#define UART0_SCR_REG (*(PVUB)(UART0_SCR)) // SCR Scratch Register
#define UART0_IRCR_REG (*(PVUB)(UART0_IRCR))// IRCR IrDA Control Register
#define UART0_CURR_PTR_RX_REG (*(PVUS)(UART0_CURR_PTR_RX)) // UART -DMA RCV Current Pointer register
#define UART0_CONFIG_RX_REG (*(PVUS)(UART0_CONFIG_RX)) // UART -RCV DMA Configuration register
#define UART0_START_ADDR_HI_RX_REG (*(PVUS)(UART0_START_ADDR_HI_RX)) // UART -RCV DMA Start Page register
#define UART0_START_ADDR_LO_RX_REG (*(PVUS)(UART0_START_ADDR_LO_RX)) // UART -RCV DMA Start Address register
#define UART0_COUNT_RX_REG (*(PVUS)(UART0_COUNT_RX)) // UART -RCV DMA Count register
#define UART0_NEXT_DESCR_RX_REG (*(PVUS)(UART0_NEXT_DESCR_RX)) // UART -RCV DMA Next Descriptor Pointer register
#define UART0_DESCR_RDY_RX_REG (*(PVUS)(UART0_DESCR_RDY_RX)) // UART -RCV DMA Descriptor Ready
#define UART0_IRQSTAT_RX_REG (*(PVUS)(UART0_IRQSTAT_RX)) // UART -RCV DMA Interrupt Register
#define UART0_CURR_PTR_TX_REG (*(PVUS)(UART0_CURR_PTR_TX)) // UART -XMT DMA Current Pointer register
#define UART0_CONFIG_TX_REG (*(PVUS)(UART0_CONFIG_TX)) // UART -XMT DMA Configuration register
#define UART0_START_ADDR_HI_TX_REG (*(PVUS)(UART0_START_ADDR_HI_TX)) // UART -XMT DMA Start Page register
#define UART0_START_ADDR_LO_TX_REG (*(PVUS)(UART0_START_ADDR_LO_TX)) // UART -XMT DMA Start Address register
#define UART0_COUNT_TX_REG (*(PVUS)(UART0_COUNT_TX)) // UART -XMT DMA Count register
#define UART0_NEXT_DESCR_TX_REG (*(PVUS)(UART0_NEXT_DESCR_TX)) // UART -XMT DMA Next Descriptor Pointer register
#define UART0_DESCR_RDY_TX_REG (*(PVUS)(UART0_DESCR_RDY_TX)) // UART -XMT DMA Descriptor Ready
#define UART0_IRQSTAT_TX_REG (*(PVUS)(UART0_IRQSTAT_TX)) // UART -XMT DMA Interrupt register
/*==================================================================================
// UART 1 Controller (0xFFC0 1C00-0xFFC0 1FFF)
====================================================================================*/
#define UART1_THR_REG (*(PVUB)(UART1_THR)) // Transmit Holding register
#define UART1_RBR_REG (*(PVUB)(UART1_RBR)) // Receive Buffer register
#define UART1_DLL_REG (*(PVUB)(UART1_DLL)) // Divisor Latch (Low-Byte)
#define UART1_IER_REG (*(PVUB)(UART1_IER)) // Interrupt Enable Register
#define UART1_DLH_REG (*(PVUB)(UART1_DLH)) // Divisor Latch (High-Byte)
#define UART1_IIR_REG (*(PVUB)(UART1_IIR)) // Interrupt Identification Register
#define UART1_LCR_REG (*(PVUB)(UART1_LCR)) // Line Control Register
#define UART1_MCR_REG (*(PVUB)(UART1_MCR)) // Module Control Register
#define UART1_LSR_REG (*(PVUB)(UART1_LSR)) // Line Status Register
#define UART1_MSR_REG (*(PVUB)(UART1_MSR)) // MSR Modem Status Register
#define UART1_SCR_REG (*(PVUB)(UART1_SCR)) // SCR Scratch Register
#define UART1_CURR_PTR_RX_REG (*(PVUS)(UART1_CURR_PTR_RX)) // UART -DMA RCV Current Pointer register
#define UART1_CONFIG_RX_REG (*(PVUS)(UART1_CONFIG_RX)) // UART -RCV DMA Configuration register
#define UART1_START_ADDR_HI_RX_REG (*(PVUS)(UART1_START_ADDR_HI_RX)) // UART -RCV DMA Start Page register
#define UART1_START_ADDR_LO_RX_REG (*(PVUS)(UART1_START_ADDR_LO_RX)) // UART -RCV DMA Start Address register
#define UART1_COUNT_RX_REG (*(PVUS)(UART1_COUNT_RX)) // UART -RCV DMA Count register
#define UART1_NEXT_DESCR_RX_REG (*(PVUS)(UART1_NEXT_DESCR_RX)) // UART -RCV DMA Next Descriptor Pointer register
#define UART1_DESCR_RDY_RX_REG (*(PVUS)(UART1_DESCR_RDY_RX)) // UART -RCV DMA Descriptor Ready
#define UART1_IRQSTAT_RX_REG (*(PVUS)(UART1_IRQSTAT_RX)) // UART -RCV DMA Interrupt Register
#define UART1_CURR_PTR_TX_REG (*(PVUS)(UART1_CURR_PTR_TX)) // UART -XMT DMA Current Pointer register
#define UART1_CONFIG_TX_REG (*(PVUS)(UART1_CONFIG_TX)) // UART -XMT DMA Configuration register
#define UART1_START_ADDR_HI_TX_REG (*(PVUS)(UART1_START_ADDR_HI_TX)) // UART -XMT DMA Start Page register
#define UART1_START_ADDR_LO_TX_REG (*(PVUS)(UART1_START_ADDR_LO_TX)) // UART -XMT DMA Start Address register
#define UART1_COUNT_TX_REG (*(PVUS)(UART1_COUNT_TX)) // UART -XMT DMA Count register
#define UART1_NEXT_DESCR_TX_REG (*(PVUS)(UART1_NEXT_DESCR_TX)) // UART -XMT DMA Next Descriptor Pointer register
#define UART1_DESCR_RDY_TX_REG (*(PVUS)(UART1_DESCR_RDY_TX)) // UART -XMT DMA Descriptor Ready
#define UART1_IRQSTAT_TX_REG (*(PVUS)(UART1_IRQSTAT_TX)) // UART -XMT DMA Interrupt register
/*==================================================================================
// TIMER 0, 1, 2 Registers (0xFFC0 2000-0xFFC0 23FF)
====================================================================================*/
#define TIMER0_STATUS_REG (*(PVUS)(TIMER0_STATUS)) // Timer 0 Global Status and Sticky Register
#define TIMER0_CONFIG_REG (*(PVUS)(TIMER0_CONFIG)) // Timer 0 configuration Register
#define TIMER0_COUNTER_LO_REG (*(PVUS)(TIMER0_COUNTER_LO)) // Timer 0 Counter Register (low word)
#define TIMER0_COUNTER_HI_REG (*(PVUS)(TIMER0_COUNTER_HI)) // Timer 0 Counter Register (high word)
#define TIMER0_PERIOD_LO_REG (*(PVUS)(TIMER0_PERIOD_LO)) // Timer 0 Period Register (low word)
#define TIMER0_PERIOD_HI_REG (*(PVUS)(TIMER0_PERIOD_HI)) // Timer 0 Period Register (high word)
#define TIMER0_WIDTH_LO_REG (*(PVUS)(TIMER0_WIDTH_LO)) // Timer 0 Width Register (low word)
#define TIMER0_WIDTH_HI_REG (*(PVUS)(TIMER0_WIDTH_HI)) // Timer 0 Width Register (high word)
#define TIMER1_STATUS_REG (*(PVUS)(TIMER1_STATUS)) // Timer 1 Global Status and Sticky Register
#define TIMER1_CONFIG_REG (*(PVUS)(TIMER1_CONFIG)) // Timer 1 configuration register
#define TIMER1_COUNTER_LO_REG (*(PVUS)(TIMER1_COUNTER_LO)) // Timer 1 Counter Register (low word)
#define TIMER1_COUNTER_HI_REG (*(PVUS)(TIMER1_COUNTER_HI)) // Timer 1 Counter Register (high word)
#define TIMER1_PERIOD_LO_REG (*(PVUS)(TIMER1_PERIOD_LO)) // Timer 1 Period Register (low word)
#define TIMER1_PERIOD_HI_REG (*(PVUS)(TIMER1_PERIOD_HI)) // Timer 1 Period Register (high word)
#define TIMER1_WIDTH_LO_REG (*(PVUS)(TIMER1_WIDTH_LO)) // Timer 1 Width Register (low word)
#define TIMER1_WIDTH_HI_REG (*(PVUS)(TIMER1_WIDTH_HI)) // Timer 1 Width Register (high word)
#define TIMER2_STATUS_REG (*(PVUS)(TIMER2_STATUS)) // Timer 2 Global Status and Sticky Register
#define TIMER2_CONFIG_REG (*(PVUS)(TIMER2_CONFIG)) // Timer 2 configuration register
#define TIMER2_COUNTER_LO_REG (*(PVUS)(TIMER2_COUNTER_LO)) // Timer 2 Counter Register (low word)
#define TIMER2_COUNTER_HI_REG (*(PVUS)(TIMER2_COUNTER_HI)) // Timer 2 Counter Register (high word)
#define TIMER2_PERIOD_LO_REG (*(PVUS)(TIMER2_PERIOD_LO)) // Timer 2 Period Register (low word)
#define TIMER2_PERIOD_HI_REG (*(PVUS)(TIMER2_PERIOD_HI)) // Timer 2 Period Register (high word)
#define TIMER2_WIDTH_LO_REG (*(PVUS)(TIMER2_WIDTH_LO)) // Timer 2 Width Register (low word)
#define TIMER2_WIDTH_HI_REG (*(PVUS)(TIMER2_WIDTH_HI)) // Timer 2 Width Register (high word)
/*==================================================================================
// General Purpose IO (0xFFC0 2400-0xFFC0 27FF)
====================================================================================*/
#define FIO_DIR_REG (*(PVUS)(FIO_DIR)) // Peripheral Flag Direction Register
#define FIO_FLAG_C_REG (*(PVUS)(FIO_FLAG_C)) // Peripheral Interrupt Flag Register (clear)
#define FIO_FLAG_S_REG (*(PVUS)(FIO_FLAG_S)) // Peripheral Interrupt Flag Register (set)
#define FIO_MASKA_C_REG (*(PVUS)(FIO_MASKA_C)) // Flag Mask Interrupt A Register (clear)
#define FIO_MASKA_S_REG (*(PVUS)(FIO_MASKA_S)) // Flag Mask Interrupt A Register (set)
#define FIO_MASKB_C_REG (*(PVUS)(FIO_MASKB_C)) // Flag Mask Interrupt B Register (clear)
#define FIO_MASKB_S_REG (*(PVUS)(FIO_MASKB_S)) // Flag Mask Interrupt B Register (set)
#define FIO_POLAR_REG (*(PVUS)(FIO_POLAR)) // Flag Source Polarity Register
#define FIO_EDGE_REG (*(PVUS)(FIO_EDGE)) // Flag Source Sensitivity Register
#define FIO_BOTH_REG (*(PVUS)(FIO_BOTH)) // Flag Set on BOTH Edges Register
/*==================================================================================
// SPORT0 Controller (0xFFC0 2800-0xFFC0 2BFF)
====================================================================================*/
#define SPORT0_TX_CONFIG_REG (*(PVUS)(SPORT0_TX_CONFIG)) // SPORT0 Transmit Configuration Register
#define SPORT0_RX_CONFIG_REG (*(PVUS)(SPORT0_RX_CONFIG)) // SPORT0 Receive Configuration Register
#define SPORT0_TX_REG (*(PVUS)(SPORT0_TX)) // SPORT0 TX transmit Register
#define SPORT0_RX_REG (*(PVUS)(SPORT0_RX)) // SPORT0 RX Receive register
#define SPORT0_TSCLKDIV_REG (*(PVUS)(SPORT0_TSCLKDIV)) // SPORT0 Transmit Serial Clock Divider
#define SPORT0_RSCLKDIV_REG (*(PVUS)(SPORT0_RSCLKDIV)) // SPORT0 Receive Serial Clock Divider
#define SPORT0_TFSDIV_REG (*(PVUS)(SPORT0_TFSDIV)) // SPORT0 Transmit Frame Sync Divider
#define SPORT0_RFSDIV_REG (*(PVUS)(SPORT0_RFSDIV)) // SPORT0 Receive Frame Sync Divider
#define SPORT0_STAT_REG (*(PVUS)(SPORT0_STAT)) /// SPORT0 Status Register
#define SPORT0_MTCS0_REG (*(PVUS)(SPORT0_MTCS0)) // SPORT0 Multi-Channel Transmit Select Register
#define SPORT0_MTCS1_REG (*(PVUS)(SPORT0_MTCS1)) // SPORT0 Multi-Channel Transmit Select Register
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