#define	bTxICLK  1
#define	bTxDTYPE 2
#define	bTxSENDN 4
#define	bTxSLEN  5
#define	bTxITFS  9
#define	bTxTFSR  10
#define	bTxDITFS 11
#define	bTxLTFS  12
#define	bTxLATFS 13
#define	bTxCKFE  14
#define	bTxICLKD 15

//..............................................................................

// SPORTx_RX_CONFIG 

#define	bRxRSPEN 0
#define	bRxICLK  1
#define	bRxDTYPE 2
#define	bRxSENDN 4
#define	bRxSLEN  5
#define	bRxIRFS  9
#define	bRxRFSR  10
#define	bRxLRFS  12
#define	bRxLARFS 13
#define	bRxCKFE  14
#define	bRxICLKD 15

//..............................................................................
// SPORTx_STAT
#define bROVF 0
#define bRXS 1
#define bTXS 2
#define bTUVF 3
#define bCHNL 4

//..............................................................................
// SPORTx_IRQSTAT_RX

#define bRxCOMPL  0 
#define bRxERR    1
#define bRxBUSERR 2

// SPORTx_IRQSTAT_TX

#define bTxCOMPL  0 
#define bTxERR    1
#define bTxBUSERR 2
 
// SPORTx_MCMC1

#define bMCM   0
#define bMFD   1
#define bWSIZE 5
#define bWOFF  9

// SPORTx_MCMC2

#define bMCCRM   0
#define bMCDTXPE 2
#define bMCDRXPE 3
#define bMCOM    4
#define bMCFF    5
#define bFSDR    7

// SPORTx_CONFIG_DMA_TX

#define bTxDEN   0
#define bTxTRAN  1
#define bTxDCOME 2
#define bTxDSB0  3
#define bTxDAUTO 4
#define bTxFLSH  7
#define bTxDERE  8
#define bTxTUVF  9
#define bTxDSB1  12
#define bTxFS    12
#define bTxDS    14
#define bTxDOWN  15

#define kTxDAUTO   ZET(bTxDAUTO,1) 

// SPORTx_CONFIG_DMA_RX

#define bRxDEN   0
#define bRxTRAN  1
#define bRxDCOME 2
#define bRxDSB0  3
#define bRxDAUTO 4
#define bRxFLSH  7
#define bRxDERE  8
#define bRxROVF  9
#define bRxDSB1  12
#define bRxFS    12
#define bRxDS    14
#define bRxDOWN  15



// EBIU_SDRRC

#define	kSDRRC	\
		ZET(bEBIU_RDIV,2071)  /* RDIV */


// ] [ No-name DIMM, 64M, 1 row, 8 chips (?)

#define START_EXT_L2SDRAM (ULONG *)0x0
#define END_EXT_L2SDRAM (ULONG *)0x04000000 // 64 MByte DIMM PC-133

// EBIU_SDRRC

#define bEBIU_RDIV 0

// EBIU_SDBCTL

#define bEBIU_EB0E   0
#define bEBIU_EB0SZ  1
#define bEBIU_EB0CAW 4
#define bEBIU_EB1E   8
#define bEBIU_EB1SZ  9
#define bEBIU_EB1CAW 12
#define bEBIU_EB2E   16
#define bEBIU_EB2SZ  17
#define bEBIU_EB2CAW 20
#define bEBIU_EB3E   24
#define bEBIU_EB3SZ  25
#define bEBIU_EB3CAW 28


// EBIU_SDGCTL

#define bEBIU_SCTLE 0
#define bEBIU_SCK1E 1
#define bEBIU_CL    2
#define bEBIU_PFE   4
#define bEBIU_PFP   5
#define bEBIU_TRAS  6
#define bEBIU_TRP   11
#define bEBIU_TRCD  15
#define bEBIU_TWR   19
#define bEBIU_PSM   22
#define bEBIU_PSSE  23
#define bEBIU_SRFS  24
#define bEBIU_EBUFE 25
#define bEBIU_X16DE 31


// EBIU_SDBCTL

#define	kSDBCTL	\
		ZET(bEBIU_EB0E,1)+    /* SDRAM external bank 0 enable */       \
		ZET(bEBIU_EB0SZ,1)+   /* SDRAM external bank 0 32 MB */        \
		ZET(bEBIU_EB0CAW,1)+  /* Bank 0 column address width 9 bits */ \
		ZET(bEBIU_EB1E,1)+    /* SDRAM external bank 1 enable */       \
		ZET(bEBIU_EB1SZ,1)+   /* SDRAM external bank 1 32 MB */        \
		ZET(bEBIU_EB1CAW,1)+  /* Bank 1 column address width 9 bits */ \
		ZET(bEBIU_EB2E,0)+    /* SDRAM external bank 2 enable */      \
		ZET(bEBIU_EB2SZ,1)+   /* SDRAM external bank 2 32 MB */        \
		ZET(bEBIU_EB2CAW,1)+  /* Bank 2 column address width 9 bits */ \
		ZET(bEBIU_EB3E,0)+    /* SDRAM external bank 3 enable */      \
		ZET(bEBIU_EB3SZ,1)+   /* SDRAM external bank 3 32 MB */        \
		ZET(bEBIU_EB3CAW,1)   /* Bank 3 column address width 9 bits */             

// EBIU_SDGCTL

#define kSDGCTL \
		ZET(bEBIU_SCTLE,1)+   \
                                  /* Enable SCLK[0],SRAS,SCAS,SWE,SDQM[3:0] */ \
		ZET(bEBIU_SCK1E,1)+   /* Enable SCLK[1] */                     \
		ZET(bEBIU_CL,2)+      /* SDRAM CAS latency 2 cycles */         \
		ZET(bEBIU_PFE,1)+     /* SDRAM prefetch enable */              \
		ZET(bEBIU_PFP,1)+     /* Prefetch priority over AMC requests*/ \
		ZET(bEBIU_TRAS,7)+    /* SDRAM tRAS in SCLK cycles */          \
		ZET(bEBIU_TRP,3)+     /* SDRAM tRP in SCLK cycles */           \
		ZET(bEBIU_TRCD,3)+    /* SDRAM tRCD in SCLK cycles */          \
		ZET(bEBIU_TWR,2)+     /* SDRAM tWR in SCLK cycles */           \
		ZET(bEBIU_PSM,0)+     /* SDRAM power-up sequence, */           \
           /* Precharge, 8 CBR refresh cycles, mode register set  */           \
		ZET(bEBIU_PSSE,1)+    /* Enables SDRAM power-up sequence */    \
                                      /* on next SDRAM access. */              \
		ZET(bEBIU_SRFS,0)+    /* SDRAM self-refresh mode start, */     \
                                      /* no effect */                          \
		ZET(bEBIU_EBUFE,0)+   /* External buffering timing disabled */ \
		ZET(bEBIU_X16DE,0)    /* SDRAM external datapath width 32 bits*/     


#endif