?? regs_gpio.h
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/*======================================================================= * * FILE: regs_gpio.h * * DESCRIPTION: GPIO Register Definition * * Copyright Cirrus Logic, 2001-2002 * *======================================================================= */#ifndef _REGS_GPIO_H_#define _REGS_GPIO_H_typedef union { struct { unsigned int Px0DATA:1; unsigned int Px1DATA:1; unsigned int Px2DATA:1; unsigned int Px3DATA:1; unsigned int Px4DATA:1; unsigned int Px5DATA:1; unsigned int Px6DATA:1; unsigned int Px7DATA:1; unsigned int RSVD:24; } Field; unsigned int Value;} GPIO_DATA_REG_TYPE;typedef union { struct { unsigned int Px0DIR:1; unsigned int Px1DIR:1; unsigned int Px2DIR:1; unsigned int Px3DIR:1; unsigned int Px4DIR:1; unsigned int Px5DIR:1; unsigned int Px6DIR:1; unsigned int Px7DIR:1; unsigned int RSVD:24; } Field; unsigned int Value;} GPIO_DATA_DIR_REG_TYPE;typedef union { struct { unsigned int PxINT0:1; unsigned int PxINT1:1; unsigned int PxINT2:1; unsigned int PxINT3:1; unsigned int PxINT4:1; unsigned int PxINT5:1; unsigned int PxINT6:1; unsigned int PxINT7:1; unsigned int RSVD:24; } Field; unsigned int Value;} GPIO_INT_EN_REG_TYPE;typedef union { struct { unsigned int Px0INTE:1; unsigned int Px1INTE:1; unsigned int Px2INTE:1; unsigned int Px3INTE:1; unsigned int Px4INTE:1; unsigned int Px5INTE:1; unsigned int Px6INTE:1; unsigned int Px7INTE:1; unsigned int RSVD:24; } Field; unsigned int Value;} GPIO_INT_TYPE1_REG_TYPE;typedef union { struct { unsigned int Px0INTR:1; unsigned int Px1INTR:1; unsigned int Px2INTR:1; unsigned int Px3INTR:1; unsigned int Px4INTR:1; unsigned int Px5INTR:1; unsigned int Px6INTR:1; unsigned int Px7INTR:1; unsigned int RSVD:24; } Field; unsigned int Value;} GPIO_INT_TYPE2_REG_TYPE;typedef unsigned int GPIO_EOI_TYPE; // write onlytypedef union { struct { unsigned int D0:1; unsigned int D1:1; unsigned int D2:1; unsigned int D3:1; unsigned int D4:1; unsigned int D5:1; unsigned int D6:1; unsigned int D7:1; unsigned int RSVD:24; } Field; unsigned int Value;} GPIO_DEBOUNCE_REG_TYPE, GPIO_INT_STATUS_TYPE;typedef struct tGPIO{ // Data Registers and Data Direction Registers for // GPIO ports A-H GPIO_DATA_REG_TYPE PADR; // 0000 GPIO_DATA_REG_TYPE PBDR; // 0004 GPIO_DATA_REG_TYPE PCDR; // 0008 GPIO_DATA_REG_TYPE PDDR; // 000C GPIO_DATA_DIR_REG_TYPE PADDR; // 0010 GPIO_DATA_DIR_REG_TYPE PBDDR; // 0014 GPIO_DATA_DIR_REG_TYPE PCDDR; // 0018 GPIO_DATA_DIR_REG_TYPE PDDDR; // 001C GPIO_DATA_REG_TYPE PEDR; // 0020 GPIO_DATA_DIR_REG_TYPE PEDDR; // 0024 unsigned int const RESERVED1; // 0028 unsigned int const RESERVED2; // 002C GPIO_DATA_REG_TYPE PFDR; // 0030 GPIO_DATA_DIR_REG_TYPE PFDDR; // 0034 GPIO_DATA_REG_TYPE PGDR; // 0038 GPIO_DATA_DIR_REG_TYPE PGDDR; // 003C GPIO_DATA_REG_TYPE PHDR; // 0040 GPIO_DATA_DIR_REG_TYPE PHDDR; // 0044 unsigned int const RESERVED3; // 0048 // // GPIO Port F interrupt and debounce registers // GPIO_INT_TYPE1_REG_TYPE GPIOFINTTYPE1; // 004C GPIO_INT_TYPE2_REG_TYPE GPIOFINTTYPE2; // 0050 GPIO_EOI_TYPE GPIOFEOI; // 0054 - write only GPIO_INT_EN_REG_TYPE GPIOFINTEN; // 0058 GPIO_INT_STATUS_TYPE INTSTATUSF; // 005C - read only GPIO_INT_STATUS_TYPE RAWINTSTATUSF; // 0060 - read only GPIO_DEBOUNCE_REG_TYPE GPIOFDB; // 0064 unsigned int const RESERVED5[(-(0x68-0x90))>>2]; // 0068 - 0090 // // GPIO Port A interrupt and debounce registers // GPIO_INT_TYPE1_REG_TYPE GPIOAINTTYPE1; // 0090 GPIO_INT_TYPE2_REG_TYPE GPIOAINTTYPE2; // 0094 GPIO_EOI_TYPE GPIOAEOI; // 0098 - write only GPIO_INT_EN_REG_TYPE GPIOAINTEN; // 009C GPIO_INT_STATUS_TYPE INTSTATUSA; // 00A0 - read only GPIO_INT_STATUS_TYPE RAWINTSTATUSA; // 00A4 - read only GPIO_DEBOUNCE_REG_TYPE GPIOADB; // 00A8 // // GPIO Port B interrupt and debounce registers // GPIO_INT_TYPE1_REG_TYPE GPIOBINTTYPE1; // 00AC GPIO_INT_TYPE2_REG_TYPE GPIOBINTTYPE2; // 00B0 GPIO_EOI_TYPE GPIOBEOI; // 00B4 - write only GPIO_INT_EN_REG_TYPE GPIOBINTEN; // 00B8 GPIO_INT_STATUS_TYPE INTSTATUSB; // 00BC - read only GPIO_INT_STATUS_TYPE RAWINTSTATUSB; // 00C0 - read only GPIO_DEBOUNCE_REG_TYPE GPIOBDB; // 00C4 union { struct { unsigned int CLKOD:1; unsigned int DATOD:1; unsigned int RSVD:30; } Field; unsigned int Value; } EEDRIVE; // 00C8 // // Test registers // unsigned int RESERVED8; // 00CC unsigned int GPIOTCR; // 00D0 unsigned int GPIOTISRA; // 00D4 unsigned int GPIOTISRB; // 00D8 unsigned int GPIOTISRC; // 00DC unsigned int GPIOTISRD; // 00E0 unsigned int GPIOTISRE; // 00E4 unsigned int GPIOTISRF; // 00E8 unsigned int GPIOTISRG; // 00EC unsigned int GPIOTISRH; // 00F0 unsigned int GPIOCER; // 00F4 } GPIO;/* union { struct { unsigned int :; } Field; unsigned int Value; } ;*///-----------------------------------------------------------------------------// Global Register Anchor Definitions//-----------------------------------------------------------------------------static volatile GPIO * const gpio = (GPIO * const)0x80840000;// typedef enum{// PortA = 0,// PortB,// PortC,// PortD,// PortE,// PortF,// PortG,// PortH// } GPIO_PORT_NUMBERS;// // typedef struct{// GPIO_DATA_REG_TYPE * const DR;// GPIO_DATA_DIR_REG_TYPE * const DDR;// GPIO_INT_TYPE1_REG_TYPE * const INT_TYPE1;// GPIO_INT_TYPE2_REG_TYPE * const INT_TYPE2;// GPIO_INT_EN_REG_TYPE * const INT_EN;// GPIO_INT_STATUS_TYPE * const INT_STATUS;// GPIO_INT_STATUS_TYPE * const RAW_INT_STATUS;// GPIO_DEBOUNCE_REG_TYPE * const DEBOUNCE;// } GPIO_REG_SET_TYPE;// // volatile GPIO_REG_SET_TYPE GPIOREG[8] =// {// // Port A// {// (GPIO_DATA_REG_TYPE * ) ( 0x80840000 + 0x00 ),// (GPIO_DATA_DIR_REG_TYPE * ) ( 0x80840000 + 0x10 ),// (GPIO_INT_TYPE1_REG_TYPE * ) ( 0x80840000 + 0x90 ),// (GPIO_INT_TYPE2_REG_TYPE * ) ( 0x80840000 + 0x94 ),// (GPIO_INT_EN_REG_TYPE * ) ( 0x80840000 + 0x9C ),// (GPIO_INT_STATUS_TYPE * ) ( 0x80840000 + 0xA0 ),// (GPIO_INT_STATUS_TYPE * ) ( 0x80840000 + 0xA4 ),// (GPIO_DEBOUNCE_REG_TYPE * ) ( 0x80840000 + 0xA8 )// },// // // Port B// {// (GPIO_DATA_REG_TYPE * ) ( 0x80840000 + 0x04 ),// (GPIO_DATA_DIR_REG_TYPE * ) ( 0x80840000 + 0x14 ),// (GPIO_INT_TYPE1_REG_TYPE * ) ( 0x80840000 + 0xAC ),// (GPIO_INT_TYPE2_REG_TYPE * ) ( 0x80840000 + 0xB0 ),// (GPIO_INT_EN_REG_TYPE * ) ( 0x80840000 + 0xB8 ),// (GPIO_INT_STATUS_TYPE * ) ( 0x80840000 + 0xBC ),// (GPIO_INT_STATUS_TYPE * ) ( 0x80840000 + 0xC0 ),// (GPIO_DEBOUNCE_REG_TYPE * ) ( 0x80840000 + 0xC4 )// },// // // Port C// {// (GPIO_DATA_REG_TYPE * ) ( 0x80840000 + 0x08 ),// (GPIO_DATA_DIR_REG_TYPE * ) ( 0x80840000 + 0x18 ),// (GPIO_INT_TYPE1_REG_TYPE * ) 0,// (GPIO_INT_TYPE2_REG_TYPE * ) 0,// (GPIO_INT_EN_REG_TYPE * ) 0,// (GPIO_INT_STATUS_TYPE * ) 0,// (GPIO_INT_STATUS_TYPE * ) 0,// (GPIO_DEBOUNCE_REG_TYPE * ) 0// },// // // Port D// {// (GPIO_DATA_REG_TYPE * ) ( 0x80840000 + 0x0C ),// (GPIO_DATA_DIR_REG_TYPE * ) ( 0x80840000 + 0x1C ),// (GPIO_INT_TYPE1_REG_TYPE * ) 0,// (GPIO_INT_TYPE2_REG_TYPE * ) 0,// (GPIO_INT_EN_REG_TYPE * ) 0,// (GPIO_INT_STATUS_TYPE * ) 0,// (GPIO_INT_STATUS_TYPE * ) 0,// (GPIO_DEBOUNCE_REG_TYPE * ) 0// },// // // Port E// {// (GPIO_DATA_REG_TYPE * ) ( 0x80840000 + 0x20 ),// (GPIO_DATA_DIR_REG_TYPE * ) ( 0x80840000 + 0x24 ),// (GPIO_INT_TYPE1_REG_TYPE * ) 0,// (GPIO_INT_TYPE2_REG_TYPE * ) 0,// (GPIO_INT_EN_REG_TYPE * ) 0,// (GPIO_INT_STATUS_TYPE * ) 0,// (GPIO_INT_STATUS_TYPE * ) 0,// (GPIO_DEBOUNCE_REG_TYPE * ) 0// },// // // Port F// {// (GPIO_DATA_REG_TYPE * ) ( 0x80840000 + 0x30 ),// (GPIO_DATA_DIR_REG_TYPE * ) ( 0x80840000 + 0x34 ),// (GPIO_INT_TYPE1_REG_TYPE * ) ( 0x80840000 + 0x4C ),// (GPIO_INT_TYPE2_REG_TYPE * ) ( 0x80840000 + 0x50 ),// (GPIO_INT_EN_REG_TYPE * ) ( 0x80840000 + 0x58 ),// (GPIO_INT_STATUS_TYPE * ) ( 0x80840000 + 0x5C ),// (GPIO_INT_STATUS_TYPE * ) ( 0x80840000 + 0x60 ),// (GPIO_DEBOUNCE_REG_TYPE * ) ( 0x80840000 + 0x64 )// },// // // Port G// {// (GPIO_DATA_REG_TYPE * ) ( 0x80840000 + 0x38 ),// (GPIO_DATA_DIR_REG_TYPE * ) ( 0x80840000 + 0x3C ),// (GPIO_INT_TYPE1_REG_TYPE * ) 0,// (GPIO_INT_TYPE2_REG_TYPE * ) 0,// (GPIO_INT_EN_REG_TYPE * ) 0,// (GPIO_INT_STATUS_TYPE * ) 0,// (GPIO_INT_STATUS_TYPE * ) 0,// (GPIO_DEBOUNCE_REG_TYPE * ) 0// },// // // Port H// {// (GPIO_DATA_REG_TYPE * ) ( 0x80840000 + 0x40 ),// (GPIO_DATA_DIR_REG_TYPE * ) ( 0x80840000 + 0x44 ),// (GPIO_INT_TYPE1_REG_TYPE * ) 0,// (GPIO_INT_TYPE2_REG_TYPE * ) 0,// (GPIO_INT_EN_REG_TYPE * ) 0,// (GPIO_INT_STATUS_TYPE * ) 0,// (GPIO_INT_STATUS_TYPE * ) 0,// (GPIO_DEBOUNCE_REG_TYPE * ) 0// }// }; //-----------------------------------------------------------------------------// Bit definitionses//-----------------------------------------------------------------------------//=============================================================================//=============================================================================#endif /* _REGS_GPIO_H_ */?? 快捷鍵說明
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