?? regs_syscon.h
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//=============================================================================// // FILE: regs_syscon.h//// DESCRIPTION: //// Copyright Cirrus Logic Corporation, 2002. All rights reserved////=============================================================================#ifndef _REGS_SYSCON_H_#define _REGS_SYSCON_H_//=============================================================================//=============================================================================typedef struct _SYSCON{ union { struct { unsigned int RTCDIV:6; unsigned int PLL1_LOCK:1; unsigned int PLL1_LOCK_REG:1; unsigned int PLL2_LOCK:1; unsigned int PLL2_LOCK_REG:1; unsigned int SW_RESET:1; unsigned int RSTFLG:1; unsigned int TEST_RESET:1; unsigned int CLDFLG:1; unsigned int RAZ:1; unsigned int WDTFLG:1; unsigned int CHIPID:8; unsigned int CHIPMAN:8; } const Field; unsigned int Value; } PWRSR; // 0x0000 union { struct { unsigned int const RSVD0:16; unsigned int DMAM2PCH1:1; unsigned int DMAM2PCH0:1; unsigned int DMAM2PCH3:1; unsigned int DMAM2PCH2:1; unsigned int DMAM2PCH5:1; unsigned int DMAM2PCH4:1; unsigned int DMAM2PCH7:1; unsigned int DMAM2PCH6:1; unsigned int DMAM2PCH9:1; unsigned int DMAM2PCH8:1; unsigned int DMAM2MCH0:1; unsigned int DMAM2MCH1:1; unsigned int USH_EN:1; unsigned int UART_BAUD:1; unsigned int RAZ:1; unsigned int FIR_EN:1; } Field; unsigned int Value; } PWRCNT; // 0x0004 union { const unsigned int Value; } HALT; // 0x0008 union { const unsigned int Value; } STANDBY; // 0x000c unsigned char Reserved0[0x8]; union { unsigned int Value; } TEOI; // 0x0018 union { unsigned int Value; } STFCLR; // 0x001c union { unsigned int Value; } CLKSET1; // 0x0020 union { struct { unsigned int PLL2X2IPD:5; unsigned int PLL2X2FBD2:6; unsigned int PLL2X1FBD1:5; unsigned int PLL2_PS:2; unsigned int PLL2_EN:1; unsigned int nBYP2:1; unsigned int RAZ:8; unsigned int USB_DIV:4; } Field; unsigned int Value; } CLKSET2; // 0x0024 unsigned char Reserved1[0x18]; union { unsigned int Value; } SCRREG0; // 0x0040 union { unsigned int Value; } SCRREG1; // 0x0044 unsigned char Reserved2[8]; // 0x0048, 004C union { struct { unsigned int NO_WRITE_WAIT:1; unsigned int RSVD:31; } Field; unsigned int Value; } APBWAIT; // 0x0050 union { struct { unsigned int PRI_ORD:2; unsigned int RSVD0:1; unsigned int PRI_CODE:1; unsigned int DMA_ENIRQ:1; unsigned int DMA_ENFIQ:1; unsigned int USH_ENIRQ:1; unsigned int USH_ENFIQ:1; unsigned int MAC_ENIRQ:1; unsigned int MAC_ENFIQ:1; unsigned int GRAP_ENIRQ:1; unsigned int GRAP_ENFIQ:1; unsigned int RSVD:20; } Field; unsigned int Value; } BMAR; // 0x0054 union { unsigned int Value; } BOOTCLR; // 0x0058 unsigned char Reserved3[0x24]; union { // // SW Locked // unsigned int Value; } DEVCFG; // 0x0080 union { // // SW Locked // unsigned int Value; } VIDDIV; // 0x0084 union { // // SW Locked // unsigned int Value; } MIRDIV; // 0x0088 union { // // SW Locked // unsigned int Value; } I2SDIV; // 0x008c union { // // SW Locked // unsigned int Value; } KTDIV; // 0x0090 union { struct { unsigned int ID:16; unsigned int PKID:1; unsigned int RSVD0:1; unsigned int BND:1; unsigned int RSVD1:6; unsigned int FAB:3; unsigned int REV:4; } const Field; unsigned int Value; } CHIP_ID; // 0x0094 union { // // SW Locked // unsigned int Value; }TESTCR; // 0x0098 union { // // SW Locked // unsigned int Value; }SYSCFG; // 0x009c unsigned char const Reserved4[0x20]; union { unsigned int Value; } SYSLOCK; // 0x00c0/* union { struct { unsigned int :; } Field; unsigned int Value; } ;*/} SYSCON;//-----------------------------------------------------------------------------// SYSCON_CLKSET1//-----------------------------------------------------------------------------#define SYSCON_CLKSET1_PLL1_X2IPD_SHIFT 0#define SYSCON_CLKSET1_PLL1_X2IPD_MASK 0x0000001f#define SYSCON_CLKSET1_PLL1_X2FBD2_SHIFT 5#define SYSCON_CLKSET1_PLL1_X2FBD2_MASK 0x000007e0#define SYSCON_CLKSET1_PLL1_X1FBD1_SHIFT 11#define SYSCON_CLKSET1_PLL1_X1FBD1_MASK 0x0000f800#define SYSCON_CLKSET1_PLL1_PS_SHIFT 16#define SYSCON_CLKSET1_PLL1_PS_MASK 0x00030000#define SYSCON_CLKSET1_PCLKDIV_SHIFT 18#define SYSCON_CLKSET1_PCLKDIV_MASK 0x000c0000#define SYSCON_CLKSET1_HCLKDIV_SHIFT 20#define SYSCON_CLKSET1_HCLKDIV_MASK 0x00700000#define SYSCON_CLKSET1_nBYP1 0x00800000#define SYSCON_CLKSET1_SMCROM 0x01000000#define SYSCON_CLKSET1_FCLKDIV_SHIFT 25#define SYSCON_CLKSET1_FCLKDIV_MASK 0x0e000000//-----------------------------------------------------------------------------// DEV_CFG Register Defines//-----------------------------------------------------------------------------#define SYSCON_DEVCFG_SHena 0x00000001#define SYSCON_DEVCFG_KEYS 0x00000002#define SYSCON_DEVCFG_ADCPD 0x00000004#define SYSCON_DEVCFG_RAS 0x00000008#define SYSCON_DEVCFG_RASonP3 0x00000010#define SYSCON_DEVCFG_TTIC 0x00000020#define SYSCON_DEVCFG_I2SonAC97 0x00000040#define SYSCON_DEVCFG_I2SonSSP 0x00000080#define SYSCON_DEVCFG_EonIDE 0x00000100#define SYSCON_DEVCFG_PonG 0x00000200#define SYSCON_DEVCFG_GonIDE 0x00000400#define SYSCON_DEVCFG_HonIDE 0x00000800#define SYSCON_DEVCFG_HC1CEN 0x00001000#define SYSCON_DEVCFG_HC1IN 0x00002000#define SYSCON_DEVCFG_HC3CEN 0x00004000#define SYSCON_DEVCFG_HC3IN 0x00008000#define SYSCON_DEVCFG_TIN 0x00020000#define SYSCON_DEVCFG_U1EN 0x00040000#define SYSCON_DEVCFG_EXVC 0x00080000#define SYSCON_DEVCFG_U2EN 0x00100000#define SYSCON_DEVCFG_A1onG 0x00200000#define SYSCON_DEVCFG_A2onG 0x00400000#define SYSCON_DEVCFG_CPENA 0x00800000#define SYSCON_DEVCFG_U3EN 0x01000000#define SYSCON_DEVCFG_MonG 0x02000000#define SYSCON_DEVCFG_TonG 0x04000000#define SYSCON_DEVCFG_GonK 0x08000000#define SYSCON_DEVCFG_IonU2 0x10000000#define SYSCON_DEVCFG_D0onG 0x20000000#define SYSCON_DEVCFG_D1onG 0x40000000#define SYSCON_DEVCFG_SWRST 0x80000000//-----------------------------------------------------------------------------// VIDDIV Register Defines//-----------------------------------------------------------------------------#define SYSCON_VIDDIV_VDIV_MASK 0x0000007f #define SYSCON_VIDDIV_VDIV_SHIFT 0#define SYSCON_VIDDIV_PDIV_MASK 0x00000300#define SYSCON_VIDDIV_PDIV_SHIFT 8#define SYSCON_VIDDIV_PSEL 0x00002000#define SYSCON_VIDDIV_ESEL 0x00004000#define SYSCON_VIDDIV_VENA 0x00008000//-----------------------------------------------------------------------------// MIRDIV Register Defines//-----------------------------------------------------------------------------#define SYSCON_MIRDIV_MDIV_MASK 0x0000003f#define SYSCON_MIRDIV_MDIV_SHIFT 0#define SYSCON_MIRDIV_PDIV_MASK 0x00000300#define SYSCON_MIRDIV_PDIV_SHIFT 8#define SYSCON_MIRDIV_PSEL 0x00002000 #define SYSCON_MIRDIV_ESEL 0x00004000#define SYSCON_MIRDIV_MENA 0x00008000//-----------------------------------------------------------------------------// I2SDIV Register Defines//-----------------------------------------------------------------------------#define SYSCON_I2SDIV_MDIV_MASK 0x0000003f#define SYSCON_I2SDIV_MDIV_SHIFT 0#define SYSCON_I2SDIV_PDIV_MASK 0x00000300#define SYSCON_I2SDIV_PDIV_SHIFT 8#define SYSCON_I2SDIV_PSEL 0x00002000#define SYSCON_I2SDIV_ESEL 0x00004000#define SYSCON_I2SDIV_MENA 0x00008000#define SYSCON_I2SDIV_SDIV 0x00010000#define SYSCON_I2SDIV_LRDIV_MASK 0x00060000#define SYSCON_I2SDIV_LRDIV_SHIFT 17#define SYSCON_I2SDIV_SPOL 0x00080000#define SYSCON_I2SDIV_DROP 0x00100000#define SYSCON_I2SDIV_ORIDE 0x20000000#define SYSCON_I2SDIV_SLAVE 0x40000000#define SYSCON_I2SDIV_SENA 0x80000000//-----------------------------------------------------------------------------// KTDIV Register Defines//-----------------------------------------------------------------------------#define SYSCON_KTDIV_KDIV 0x00000001#define SYSCON_KTDIV_KEN 0x00008000#define SYSCON_KTDIV_ADIV 0x00010000#define SYSCON_KTDIV_TSEN 0x80000000//-----------------------------------------------------------------------------// CHIPID Register Defines//-----------------------------------------------------------------------------#define SYSCON_CHIPID_ID_MASK 0x0000ffff#define SYSCON_CHIPID_ID_SHIFT 0#define SYSCON_CHIPID_PKID 0x00010000#define SYSCON_CHIPID_BND 0x00040000#define SYSCON_CHIPID_FAB_MASK 0x0e000000#define SYSCON_CHIPID_FAB_SHIFT 25#define SYSCON_CHIPID_REV_MASK 0xf0000000#define SYSCON_CHIPID_REV_SHIFT 28//-----------------------------------------------------------------------------// TESTCR Register Defines//-----------------------------------------------------------------------------#define SYSCON_TESTCR_TMODE_MASK 0x000000ff#define SYSCON_TESTCR_TMODE_SHIFT 0#define SYSCON_TESTCR_BONDO 0x00000100#define SYSCON_TESTCR_PACKO 0x00000800#define SYSCON_TESTCR_ETOM 0x00002000#define SYSCON_TESTCR_TOM 0x00004000#define SYSCON_TESTCR_OVR 0x00008000#define SYSCON_TESTCR_TonIDE 0x00010000#define SYSCON_TESTCR_RonG 0x00020000//-----------------------------------------------------------------------------// SYSCFG Register Defines//-----------------------------------------------------------------------------#define SYSCON_SYSCFG_LCSn1 0x00000001#define SYSCON_SYSCFG_LCSn2 0x00000002#define SYSCON_SYSCFG_LCSn3 0x00000004#define SYSCON_SYSCFG_LEECK 0x00000008#define SYSCON_SYSCFG_LEEDA 0x00000010#define SYSCON_SYSCFG_LASDO 0x00000020#define SYSCON_SYSCFG_LCSn6 0x00000040#define SYSCON_SYSCFG_LCSn7 0x00000080#define SYSCON_SYSCFG_SBOOT 0x00000100#define SYSCON_SYSCFG_FAB_MASK 0x0e000000#define SYSCON_SYSCFG_FAB_SHIFT 25#define SYSCON_SYSCFG_REV_MASK 0xf0000000#define SYSCON_SYSCFG_REV_SHIFT 28//-----------------------------------------------------------------------------// PWRSR Register Defines//-----------------------------------------------------------------------------#define SYSCON_PWRSR_CHIPMAN_MASK 0xFF000000#define SYSCON_PWRSR_CHIPMAN_SHIFT 24#define SYSCON_PWRSR_CHIPID_MASK 0x00FF0000#define SYSCON_PWRSR_CHIPID_SHIFT 16#define SYSCON_PWRSR_WDTFLG 0x00008000#define SYSCON_PWRSR_CLDFLG 0x00002000#define SYSCON_PWRSR_TEST_RESET 0x00001000#define SYSCON_PWRSR_RSTFLG 0x00000800#define SYSCON_PWRSR_SWRESET 0x00000400#define SYSCON_PWRSR_PLL2_LOCKREG 0x00000200#define SYSCON_PWRSR_PLL2_LOCK 0x00000100#define SYSCON_PWRSR_PLL1_LOCKREG 0x00000080 #define SYSCON_PWRSR_PLL1_LOCK 0x00000040 #define SYSCON_PWRSR_RTCDIV 0x0000003F//-----------------------------------------------------------------------------// PWRCNT Register Defines//-----------------------------------------------------------------------------#define SYSCON_PWRCNT_FIREN 0x80000000#define SYSCON_PWRCNT_UARTBAUD 0x20000000#define SYSCON_PWRCNT_USHEN 0x10000000#define SYSCON_PWRCNT_DMA_M2MCH1 0x08000000#define SYSCON_PWRCNT_DMA_M2MCH0 0x04000000#define SYSCON_PWRCNT_DMA_M2PCH8 0x02000000#define SYSCON_PWRCNT_DMA_M2PCH7 0x01000000#define SYSCON_PWRCNT_DMA_M2PCH6 0x00800000#define SYSCON_PWRCNT_DMA_M2PCH5 0x00400000#define SYSCON_PWRCNT_DMA_M2PCH4 0x00200000#define SYSCON_PWRCNT_DMA_M2PCH3 0x00010000#define SYSCON_PWRCNT_DMA_M2PCH2 0x00080000#define SYSCON_PWRCNT_DMA_M2PCH1 0x00040000#define SYSCON_PWRCNT_DMA_M2PCH0 0x00020000//-----------------------------------------------------------------------------// BMAR Register Defines//-----------------------------------------------------------------------------#define BMAR_PRIORD_00 0x00000000#define BMAR_PRIORD_01 0x00000001#define BMAR_PRIORD_02 0x00000002#define BMAR_PRIORD_03 0x00000003#define BMAR_PRI_CORE 0x00000008#define BMAR_DMA_ENIRQ 0x00000010#define BMAR_DMA_ENFIQ 0x00000020#define BMAR_USB_ENIRQ 0x00000040#define BMAR_USB_ENFIQ 0x00000080#define BMAR_MAC_ENIRQ 0x00000100#define BMAR_MAC_ENFIQ 0x00000200#define BMAR_GRAPHICS_ENIRQ 0x00000400#define BMAR_GRAPHICS_ENFIQ 0x00000800static volatile SYSCON * const SysConCSC = (SYSCON *)0x80930000;#endif // _REGS_SYSCON_H_?? 快捷鍵說明
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