目的和要求：
   1．有mr(主紅)、my（主黃）、mg（主綠）、cr（鄉紅）、cy（鄉黃）、cg（鄉綠）六盞交通燈需要控制；
   2．交通燈由綠→紅有4秒黃燈亮的間隔時間，由紅→綠沒有間隔時間；
   3．系統有mrcy、mrcg、mycr、mgcr四個狀態；
   4．相間公路右側各埋有一個傳感器，當有車輛通過相間公路時，發出請求信號s；
   5．平時系統停留在mgcr狀態，一旦s信號有效，經mrcy轉入mrcg狀態，但要保證mrcg狀態也不得短于一分鐘；
   6．一旦s信號無效，系統脫離mrcg狀態。隨即經mrcy轉入進入mgcr狀態，計時s信號一直有效，mrcg狀態也不得長于20秒鐘。

實驗儀器：gw/48系列eda開發系統(包含ep1k30tc144-3)；
編程環境：maxplus ii 10.2

vhdl程序： 分為三個底層文件和一個頂層文件：

1.控制模塊――controlm.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity controlm is
  port (clk0,reset0,s0,c0  :in std_logic;
        ld0                :out std_logic;
        dinl0,dinh0        :out std_logic_vector(3 downto 0);
        state0             :out std_logic_vector(1 downto 0));
end controlm;
architecture behav of controlm is
  signal statenum:std_logic_vector(1 downto 0);
  signal ldt:std_logic;
  signal  reg:std_logic_vector(3 downto 0);
 begin
 state0<=statenum;
 ld0<=ldt;
 reg<=statenum&s0&c0;
 process(reg,clk0)
   begin
     if reset0='0' then
       statenum<="00";dinh0<="0101";dinl0<="1001";ldt<='0'; 
     elsif clk0'event and clk0='0' then        
        case reg is
          when "0100"|"0101"|"1101"|"1111"=> statenum<="00";dinh0<="0101";dinl0<="1001";ldt<='0';
          when "1000"|"1001"|"1011"       => statenum<="11";dinh0<="0000";dinl0<="0011";ldt<='0';
          when "0011"                     => statenum<="01";dinh0<="0000";dinl0<="0011";ldt<='0';
          when "0111"                     => statenum<="10";dinh0<="0001";dinl0<="1001";ldt<='0';
          when others                     => ldt<='1';
        end case;
     end if;
end process;
end behav;

2.計數模塊－－mvc.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mvc is
  port(   cp1:in std_logic;
          ld1:in std_logic;
        dinl1:in std_logic_vector(3 downto 0);
        dinh1:in std_logic_vector(3 downto 0);
          ql1:out std_logic_vector(3 downto 0);
          qh1:out std_logic_vector(3 downto 0);
           c1:out std_logic);
end mvc;

architecture w of mvc is
signal qa,qat:std_logic_vector(3 downto 0);
signal qb,qbt:std_logic_vector(3 downto 0);
signal ca,cb :std_logic;

begin
  qh1<=qb;
  ql1<=qa;
  process(cp1)
  begin
    qat<=dinl1;
    if cp1'event and cp1='1' then
      if ld1='0' then qa<=qat;ca<='0';
      elsif(qa="0000" and qb="0000") then qa<="0000";
      elsif(qa="0000") then  qa<="1001";ca<='0';
      elsif(qa="0001") then ca<='1';qa<="0000";
      else qa<=qa-1;ca<='0';
      end if;
    end if;
  end process;

  process(ca,cp1)
  begin
    qbt<=dinh1;
    if cp1'event and cp1='1' then
      if ld1='0' then qb<=qbt;cb<='0';c1<='0';
      elsif(qb="0000" and qa="0000") then qb<="0000";
      elsif(qb="0000" and qa="0001") then c1<='1';
      elsif(ca='1')                  then  qb<=qb-1;
      end if;
    end if;
  end process;
end w;

3.信號轉換模塊――tolight.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity tolight is
  port (     clk2:in std_logic;
        statenum2:in std_logic_vector(1 downto 0);
        mr2,my2,mg2,cr2,cy2,cg2:out std_logic);
end tolight;
architecture behav of tolight is
begin
  process(clk2)
    begin
      if clk2'event and clk2='1' then
        case statenum2(1 downto 0) is
          when   "00"=>mr2<='0';my2<='0';mg2<='1';cr2<='1';cy2<='0';cg2<='0';
          when   "01"=>mr2<='0';my2<='1';mg2<='0';cr2<='1';cy2<='0';cg2<='0';
          when   "10"=>mr2<='1';my2<='0';mg2<='0';cr2<='0';cy2<='0';cg2<='1'; 
          when   "11"=>mr2<='1';my2<='0';mg2<='0';cr2<='0';cy2<='1';cg2<='0';
          when others=>mr2<='0';my2<='0';mg2<='1';cr2<='1';cy2<='0';cg2<='0';
        end case;
      end if;
  end process;
end behav;

4.頂層文件――traffic.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity traffic is
  port(   clk:in std_logic;
          s  :in std_logic;
        reset:in std_logic;
        mr,my,mg,cr,cy,cg:out std_logic;
         time:out std_logic_vector(7 downto 0));
end traffic;
architecture behav of traffic is
component controlm is
  port (clk0,reset0,s0,c0  :in std_logic;
        ld0            :out std_logic;
        dinl0,dinh0    :out std_logic_vector(3 downto 0);
        state0         :out std_logic_vector(1 downto 0));
end component controlm;
component mvc is
  port(   cp1:in  std_logic;
          ld1:in  std_logic;
        dinl1:in  std_logic_vector(3 downto 0);
        dinh1:in  std_logic_vector(3 downto 0);
          ql1:out std_logic_vector(3 downto 0);
          qh1:out std_logic_vector(3 downto 0);
           c1:out std_logic);
end component mvc;
component tolight is
  port (     clk2:in std_logic;
        statenum2:in std_logic_vector(1 downto 0);
        mr2,my2,mg2,cr2,cy2,cg2:out std_logic);
end component tolight;

signal c,ld     :std_logic;
signal dinl,dinh:std_logic_vector(3 downto 0);
signal statenum :std_logic_vector(1 downto 0);
begin
u1: controlm port map(clk0=>clk,reset0=>reset,s0=>s,c0=>c,ld0=>ld,dinl0=>dinl,dinh0=>dinh,state0=>statenum);
u2: mvc     port map(cp1=>clk,ld1=>ld,dinl1=>dinl,dinh1=>dinh,ql1=>time(3 downto 0),qh1=>time(7 downto 4),c1=>c);
u3: tolight port map(clk2=>clk,statenum2=>statenum,mr2=>mr,my2=>my,mg2=>mg,cr2=>cr,cy2=>cy,cg2=>cg);
end behav;

引腳鎖定：
根據實驗輸入輸出要求，選擇模式五作為實驗電路。
具體引腳鎖定如下：
信號名 類型 使用電路信號 引腳
clk 輸入 clock0 126
s 輸入 鍵8 19
reset 輸入 鍵7 18
mr 輸出 d8 19
my 輸出 d7 28
mg 輸出 d6 27
cr 輸出 d5 26
cy 輸出 d4 23
cg 輸出 d3 22
time(7 downto 4) 輸出 譯碼數碼管8 96．95，92，91
time(3 downto 0) 輸出 譯碼數碼管7 90，89，88，87