?? sam9_sdram.mac
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// ---------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ---------------------------------------------------------
// The software is delivered "AS IS" without warranty or
// condition of any kind, either express, implied or
// statutory. This includes without limitation any warranty
// or condition with respect to merchantability or fitness
// for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ---------------------------------------------------------
// File: SAM9_SDRAM.mac
// User setup file for CSPY debugger.
// 1.1 08/Aug/06 jpp : Creation
//
// $Revision: 1.1 $
//
// ---------------------------------------------------------
__var __mac_i;
__var __mac_pt;
/*********************************************************************
*
* execUserReset() : JTAG set initially to Full Speed
*/
execUserReset()
{
__message "------------------------------ execUserReset ---------------------------------";
CheckNoRemap();
ini();
__PllSetting100MHz();
__AIC(); //* Init AIC
__message "-------------------------------Set PC Reset ----------------------------------";
__writeMemory32(0xD3,0x98,"Register"); //* Set CPSR
__writeMemory32(0x20000000,0xB4,"Register"); //* Set PC (R15)
}
/*********************************************************************
*
* execUserPreload() : JTAG set initially to 32kHz
*/
execUserPreload()
{
__message "------------------------------ execUserPreload ---------------------------------";
__writeMemory32(0xD3,0x98,"Register"); //* Set CPSR
__PllSetting(); //* Init PLL
__PllSetting100MHz();
__initSDRAM(); //* Init SDRAM before load
__AIC(); //* Init AIC
CheckNoRemap(); //* Set the RAM memory at 0x0020 0000 & 0x0000 0000
Watchdog(); //* Watchdog Disable
//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
__mac_i=__readMemory32(0xFFFFF240,"Memory");
__message " ---------------------------------------- Chip ID 0x",__mac_i:%X;
if ( __mac_i == 0x019803A1) {__message " Chip ID for AT91SAM9260";}
else { __message " Chip ID for unknown !!";}
__mac_i=__readMemory32(0xFFFFF244,"Memory");
__message " ---------------------------------------- Extention 0x",__mac_i:%X;
}
/*********************************************************************
*
* __initSDRAM()
* Function description
* Set SDRAM for works at 100 MHz
*/
__initSDRAM()
{
//* Configure EBI Chip select
// pCCFG->CCFG_EBICSA |= AT91C_EBI_CS1A_SDRAMC;
// AT91C_CCFG_EBICSA ((AT91_REG *) 0xFFFFEF1C) // (CCFG) EBI Chip Select Assignement Register
__writeMemory32(0x0001003A,0xFFFFEF1C,"Memory");
//* Configure PIOs
//* AT91F_PIO_CfgPeriph( AT91C_BASE_PIOC, AT91C_PC16_D16 to AT91C_PC16_D31
// pPio->PIO_ASR = periphAEnable; AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register
// pPio->PIO_BSR = periphBEnable;AT91C_PIOC_BSR ((AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register
// pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
__writeMemory32(0xFFFF0000,0xFFFFF870,"Memory");
__writeMemory32(0x00000000,0xFFFFF874,"Memory");
__writeMemory32(0xFFFF0000,0xFFFFF804,"Memory");
//* psdrc->SDRAMC_CR = AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_3 |
// AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7 |
// AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8 ;
__writeMemory32(0x85227279,0xFFFFEA08,"Memory");
__sleep(100);
//* psdrc->SDRAMC_MR = 0x00000002; // Set PRCHG AL
__writeMemory32(0x00000002,0xFFFFEA00,"Memory");
//* *AT91C_SDRAM = 0x00000000; // Perform PRCHG
__writeMemory32(0x00000000,0x20000000,"Memory");
__sleep(100);
//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 1st CBR
__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
//* *(AT91C_SDRAM+4) = 0x00000001; // Perform CBR
__writeMemory32(0x00000001,0x20000010,"Memory");
//* psdrc->SDRAMC_MR = 0x00000004; // Set 2 CBR
__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
//* *(AT91C_SDRAM+8) = 0x00000002; // Perform CBR
__writeMemory32(0x00000002,0x20000020,"Memory");
//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 3 CBR
__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
//* *(AT91C_SDRAM+0xc) = 0x00000003; // Perform CBR
__writeMemory32(0x00000003,0x20000030,"Memory");
//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 4 CBR
__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
//* *(AT91C_SDRAM+0x10) = 0x00000004; // Perform CBR
__writeMemory32(0x00000004,0x20000040,"Memory");
//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 5 CBR
__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
//* *(AT91C_SDRAM+0x14) = 0x00000005; // Perform CBR
__writeMemory32(0x00000005,0x20000050,"Memory");
//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 6 CBR
__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
//* *(AT91C_SDRAM+0x18) = 0x00000006; // Perform CBR
__writeMemory32(0x00000006,0x20000060,"Memory");
//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 7 CBR
__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
//* *(AT91C_SDRAM+0x1c) = 0x00000007; // Perform CBR
__writeMemory32(0x00000007,0x20000070,"Memory");
//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 8 CBR
__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
//* *(AT91C_SDRAM+0x20) = 0x00000008; // Perform CBR
__writeMemory32(0x00000008,0x20000080,"Memory");
//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_LMR_CMD; // Set LMR operation
__writeMemory32(0x00000003,0xFFFFEA00,"Memory");
//* *(AT91C_SDRAM+0x24) = 0xcafedede; // Perform LMR burst=1, lat=2
__writeMemory32(0xCAFEDEDE,0x20000090,"Memory");
//* psdrc->SDRAMC_TR = (AT91C_MASTER_CLOCK * 7)/1000000; // Set Refresh Timer 390 for 25MHz (TR= 15.6 * F )
// // (F : system clock freq. MHz
__writeMemory32(0x000002B9,0xFFFFEA04,"Memory");
//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_NORMAL_CMD; // Set Normal mode
__writeMemory32(0x00000000,0xFFFFEA00,"Memory");
//* *AT91C_SDRAM = 0x00000000; // Perform Normal mode
__writeMemory32(0x00000000,0x20000000,"Memory");
__message "------------------------------- SDRAM Done at 100 MHz -------------------------------";
}
/*********************************************************************
*
* __PllSetting()
* Function description
* Initializes the PMC.
* 1. Enable the Main Oscillator
* 2. Configure PLL
* 3. Switch Master
*/
__PllSetting()
{
if ((__readMemory32(0xFFFFFC30,"Memory")&0x3) != 0 ) {
//* Disable all PMC interrupt ( $$ JPP)
//* AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) //(PMC) Interrupt Disable Register
//* pPmc->PMC_IDR = 0xFFFFFFFF;
__writeMemory32(0xFFFFFFFF,0xFFFFFC64,"Memory");
//* AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) //(PMC) Peripheral Clock Disable Register
__writeMemory32(0xFFFFFFFF,0xFFFFFC14,"Memory");
// Disable all clock only Processor clock is enabled.
__writeMemory32(0xFFFFFFFE,0xFFFFFC04,"Memory");
// AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
__writeMemory32(0x00000001,0xFFFFFC30,"Memory");
__sleep(10000);
// write reset value to PLLA and PLLB
// AT91C_PMC_PLLAR ((AT91_REG *) 0xFFFFFC28) // (PMC) PLL A Register
__writeMemory32(0x00003F00,0xFFFFFC28,"Memory");
// AT91C_PMC_PLLBR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL B Register
__writeMemory32(0x00003F00,0xFFFFFC2C,"Memory");
__sleep(10000);
__emulatorSpeed(0); //* Set JTAG speed to full speed
__message "------------------------------- PLL Enable -----------------------------------------";
} else {
__message " ********* Core in SLOW CLOCK mode ********* "; }
}
/*********************************************************************
*
* __PllSetting100MHz()
* Function description
* Set core at 200 MHz and MCK at 100 MHz
*/
__PllSetting100MHz()
{
__message "------------------------------- PLL Set at 100 MHz ----------------------------------";
//* pPmc->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x8 <<8) | AT91C_CKGR_MOSCEN ));
__writeMemory32(0x00000801,0xFFFFFC20,"Memory");
__sleep(10000);
// AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
__writeMemory32(0x00000001,0xFFFFFC30,"Memory");
__sleep(10000);
//* AT91C_BASE_CKGR->CKGR_PLLAR = (AT91C_CKGR_SRCA | ((172 << 16) & AT91C_CKGR_MULA) |
// (AT91C_CKGR_PLLACOUNT | (AT91C_CKGR_OUTA_2 | (16);
__writeMemory32(0x20ACBF10,0xFFFFFC28,"Memory");
__sleep(10000);
//* AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;;
__writeMemory32(0x00000102,0xFFFFFC30,"Memory");
__sleep(10000);
}
/*********************************************************************
*
* _Watchdog()
*
* Function description
* Clear Watchdog
*/
Watchdog()
{
//* Watchdog Disable
// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS;
__writeMemory32(0x00008000,0xFFFFFD44,"Memory");
__message "------------------------------- Watchdog Disable ------------------------------------";
}
/*********************************************************************
*
* CheckRemap()
*
* Function description
* Check the Remap.
*/
CheckNoRemap()
{
// AT91C_MATRIX_MRCR ((AT91_REG *) 0xFFFFEF00) // (MATRIX) Master Remp Control Register
__mac_i=__readMemory32(0xFFFFEF00,"Memory");
__message "----- AT91C_MATRIX_MRCR : 0x",__mac_i:%X;
if ( ((__mac_i & 0x01) == 0) || ((__mac_i & 0x02) == 0)){
__message "------------------------------- The Remap is NOT & REMAP ----------------------------";
__writeMemory32(0x00000003,0xFFFFEF00,"Memory");
__mac_i=__readMemory32(0xFFFFEF00,"Memory");
__message "----- AT91C_MATRIX_MRCR : 0x",__mac_i:%X;
} else {
__message "------------------------------- The Remap is done -----------------------------------";
}
}
/*********************************************************************
*
*
* Function description
* Reset the Interrupt Controller.
*/
__AIC()
{
// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;
__writeMemory32(0xffffffff,0xFFFFF124,"Memory");
__writeMemory32(0xffffffff,0xFFFFF128,"Memory");
// #define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
// #define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
// #define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
__readMemory32(0xFFFA0020,"Memory");
__readMemory32(0xFFFA0060,"Memory");
__readMemory32(0xFFFA00A0,"Memory");
// disable peripheral clock Peripheral Clock Disable Register
__writeMemory32(0xffffffff,0xFFFFFC14,"Memory");
for (__mac_i=0;__mac_i < 8; __mac_i++)
{
// AT91C_BASE_AIC->AIC_EOICR
__mac_pt = __readMemory32(0xFFFFF130,"Memory");
}
//* __message "------------------------------- AIC 2 INIT ---------------------------------------------";
}
/*********************************************************************
*
* ini() :
* Function description
* Write ARM9 core regsiter to Reset value
*/
ini()
{
__writeMemory32(0x0,0x00,"Register");
__writeMemory32(0x0,0x04,"Register");
__writeMemory32(0x0,0x08,"Register");
__writeMemory32(0x0,0x0C,"Register");
__writeMemory32(0x0,0x10,"Register");
__writeMemory32(0x0,0x14,"Register");
__writeMemory32(0x0,0x18,"Register");
__writeMemory32(0x0,0x1C,"Register");
__writeMemory32(0x0,0x20,"Register");
__writeMemory32(0x0,0x24,"Register");
__writeMemory32(0x0,0x28,"Register");
__writeMemory32(0x0,0x2C,"Register");
__writeMemory32(0x0,0x30,"Register");
__writeMemory32(0x0,0x34,"Register");
__writeMemory32(0x0,0x38,"Register");
// Set CPSR
__writeMemory32(0x0D3,0x98,"Register");
}
/*********************************************************************
*
* __Core_Register() :
* Function description
* Read all ARM9 core regsiter
*/
__Core_Register()
{
i=__readMemory32(0x00,"Register"); __message "R00 0x",i:%X;
i=__readMemory32(0x04,"Register"); __message "R01 0x",i:%X;
i=__readMemory32(0x08,"Register"); __message "R02 0x",i:%X;
i=__readMemory32(0x0C,"Register"); __message "R03 0x",i:%X;
i=__readMemory32(0x10,"Register"); __message "R04 0x",i:%X;
i=__readMemory32(0x14,"Register"); __message "R05 0x",i:%X;
i=__readMemory32(0x18,"Register"); __message "R06 0x",i:%X;
i=__readMemory32(0x1C,"Register"); __message "R07 0x",i:%X;
i=__readMemory32(0x20,"Register"); __message "R08 0x",i:%X;
i=__readMemory32(0x24,"Register"); __message "R09 0x",i:%X;
i=__readMemory32(0x28,"Register"); __message "R10 0x",i:%X;
i=__readMemory32(0x2C,"Register"); __message "R11 0x",i:%X;
i=__readMemory32(0x30,"Register"); __message "R12 0x",i:%X;
i=__readMemory32(0x34,"Register"); __message "R13 0x",i:%X;
i=__readMemory32(0x38,"Register"); __message "R14 0x",i:%X;
i=__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",i:%X;
i=__readMemory32(0x40,"Register"); __message "R14 SVC 0x",i:%X;
i=__readMemory32(0x44,"Register"); __message "R13 ABT 0x",i:%X;
i=__readMemory32(0x48,"Register"); __message "R14 ABT 0x",i:%X;
i=__readMemory32(0x4C,"Register"); __message "R13 UND 0x",i:%X;
i=__readMemory32(0x50,"Register"); __message "R14 UND 0x",i:%X;
i=__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",i:%X;
i=__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",i:%X;
i=__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",i:%X;
i=__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",i:%X;
i=__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",i:%X;
i=__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",i:%X;
i=__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",i:%X;
i=__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",i:%X;
i=__readMemory32(0x74,"Register"); __message "R14 FIQ0x",i:%X;
i=__readMemory32(0x98,"Register"); __message "CPSR ",i:%X;
i=__readMemory32(0x94,"Register"); __message "SPSR ",i:%X;
i=__readMemory32(0x9C,"Register"); __message "SPSR ABT ",i:%X;
i=__readMemory32(0xA0,"Register"); __message "SPSR ABT ",i:%X;
i=__readMemory32(0xA4,"Register"); __message "SPSR UND ",i:%X;
i=__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",i:%X;
i=__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",i:%X;
i=__readMemory32(0xB4,"Register"); __message "PC 0x",i:%X;
}
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