?? at91sam9260.tcl
字號:
set AT91C_SMC_NRDPULSE [expr 0x7F << 16 ]
set AT91C_SMC_NCSPULSERD [expr 0x7F << 24 ]
# -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x --------
set AT91C_SMC_NWECYCLE [expr 0x1FF << 0 ]
set AT91C_SMC_NRDCYCLE [expr 0x1FF << 16 ]
# -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x --------
set AT91C_SMC_READMODE [expr 0x1 << 0 ]
set AT91C_SMC_WRITEMODE [expr 0x1 << 1 ]
set AT91C_SMC_NWAITM [expr 0x3 << 5 ]
set AT91C_SMC_NWAITM_NWAIT_DISABLE [expr 0x0 << 5 ]
set AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN [expr 0x2 << 5 ]
set AT91C_SMC_NWAITM_NWAIT_ENABLE_READY [expr 0x3 << 5 ]
set AT91C_SMC_BAT [expr 0x1 << 8 ]
set AT91C_SMC_BAT_BYTE_SELECT [expr 0x0 << 8 ]
set AT91C_SMC_BAT_BYTE_WRITE [expr 0x1 << 8 ]
set AT91C_SMC_DBW [expr 0x3 << 12 ]
set AT91C_SMC_DBW_WIDTH_EIGTH_BITS [expr 0x0 << 12 ]
set AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS [expr 0x1 << 12 ]
set AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS [expr 0x2 << 12 ]
set AT91C_SMC_TDF [expr 0xF << 16 ]
set AT91C_SMC_TDFEN [expr 0x1 << 20 ]
set AT91C_SMC_PMEN [expr 0x1 << 24 ]
set AT91C_SMC_PS [expr 0x3 << 28 ]
set AT91C_SMC_PS_SIZE_FOUR_BYTES [expr 0x0 << 28 ]
set AT91C_SMC_PS_SIZE_EIGHT_BYTES [expr 0x1 << 28 ]
set AT91C_SMC_PS_SIZE_SIXTEEN_BYTES [expr 0x2 << 28 ]
set AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES [expr 0x3 << 28 ]
# -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x --------
set AT91C_SMC_NWESETUP [expr 0x3F << 0 ]
set AT91C_SMC_NCSSETUPWR [expr 0x3F << 8 ]
set AT91C_SMC_NRDSETUP [expr 0x3F << 16 ]
set AT91C_SMC_NCSSETUPRD [expr 0x3F << 24 ]
# -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x --------
set AT91C_SMC_NWEPULSE [expr 0x7F << 0 ]
set AT91C_SMC_NCSPULSEWR [expr 0x7F << 8 ]
set AT91C_SMC_NRDPULSE [expr 0x7F << 16 ]
set AT91C_SMC_NCSPULSERD [expr 0x7F << 24 ]
# -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x --------
set AT91C_SMC_NWECYCLE [expr 0x1FF << 0 ]
set AT91C_SMC_NRDCYCLE [expr 0x1FF << 16 ]
# -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x --------
set AT91C_SMC_READMODE [expr 0x1 << 0 ]
set AT91C_SMC_WRITEMODE [expr 0x1 << 1 ]
set AT91C_SMC_NWAITM [expr 0x3 << 5 ]
set AT91C_SMC_NWAITM_NWAIT_DISABLE [expr 0x0 << 5 ]
set AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN [expr 0x2 << 5 ]
set AT91C_SMC_NWAITM_NWAIT_ENABLE_READY [expr 0x3 << 5 ]
set AT91C_SMC_BAT [expr 0x1 << 8 ]
set AT91C_SMC_BAT_BYTE_SELECT [expr 0x0 << 8 ]
set AT91C_SMC_BAT_BYTE_WRITE [expr 0x1 << 8 ]
set AT91C_SMC_DBW [expr 0x3 << 12 ]
set AT91C_SMC_DBW_WIDTH_EIGTH_BITS [expr 0x0 << 12 ]
set AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS [expr 0x1 << 12 ]
set AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS [expr 0x2 << 12 ]
set AT91C_SMC_TDF [expr 0xF << 16 ]
set AT91C_SMC_TDFEN [expr 0x1 << 20 ]
set AT91C_SMC_PMEN [expr 0x1 << 24 ]
set AT91C_SMC_PS [expr 0x3 << 28 ]
set AT91C_SMC_PS_SIZE_FOUR_BYTES [expr 0x0 << 28 ]
set AT91C_SMC_PS_SIZE_EIGHT_BYTES [expr 0x1 << 28 ]
set AT91C_SMC_PS_SIZE_SIXTEEN_BYTES [expr 0x2 << 28 ]
set AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES [expr 0x3 << 28 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR AHB Matrix Interface
# *****************************************************************************
# -------- MATRIX_SCFG0 : (MATRIX Offset: 0x40) Slave Configuration Register 0 --------
set AT91C_MATRIX_SLOT_CYCLE [expr 0xFF << 0 ]
set AT91C_MATRIX_DEFMSTR_TYPE [expr 0x3 << 16 ]
set AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR [expr 0x0 << 16 ]
set AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR [expr 0x1 << 16 ]
set AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR [expr 0x2 << 16 ]
set AT91C_MATRIX_FIXED_DEFMSTR0 [expr 0x7 << 18 ]
set AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I [expr 0x0 << 18 ]
set AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D [expr 0x1 << 18 ]
set AT91C_MATRIX_FIXED_DEFMSTR0_HPDC3 [expr 0x2 << 18 ]
set AT91C_MATRIX_FIXED_DEFMSTR0_LCDC [expr 0x3 << 18 ]
set AT91C_MATRIX_FIXED_DEFMSTR0_DMA [expr 0x4 << 18 ]
# -------- MATRIX_SCFG1 : (MATRIX Offset: 0x44) Slave Configuration Register 1 --------
set AT91C_MATRIX_SLOT_CYCLE [expr 0xFF << 0 ]
set AT91C_MATRIX_DEFMSTR_TYPE [expr 0x3 << 16 ]
set AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR [expr 0x0 << 16 ]
set AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR [expr 0x1 << 16 ]
set AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR [expr 0x2 << 16 ]
set AT91C_MATRIX_FIXED_DEFMSTR1 [expr 0x7 << 18 ]
set AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I [expr 0x0 << 18 ]
set AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D [expr 0x1 << 18 ]
set AT91C_MATRIX_FIXED_DEFMSTR1_HPDC3 [expr 0x2 << 18 ]
set AT91C_MATRIX_FIXED_DEFMSTR1_LCDC [expr 0x3 << 18 ]
set AT91C_MATRIX_FIXED_DEFMSTR1_DMA [expr 0x4 << 18 ]
# -------- MATRIX_SCFG2 : (MATRIX Offset: 0x48) Slave Configuration Register 2 --------
set AT91C_MATRIX_SLOT_CYCLE [expr 0xFF << 0 ]
set AT91C_MATRIX_DEFMSTR_TYPE [expr 0x3 << 16 ]
set AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR [expr 0x0 << 16 ]
set AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR [expr 0x1 << 16 ]
set AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR [expr 0x2 << 16 ]
set AT91C_MATRIX_FIXED_DEFMSTR2 [expr 0x1 << 18 ]
set AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I [expr 0x0 << 18 ]
set AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D [expr 0x1 << 18 ]
# -------- MATRIX_SCFG3 : (MATRIX Offset: 0x4c) Slave Configuration Register 3 --------
set AT91C_MATRIX_SLOT_CYCLE [expr 0xFF << 0 ]
set AT91C_MATRIX_DEFMSTR_TYPE [expr 0x3 << 16 ]
set AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR [expr 0x0 << 16 ]
set AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR [expr 0x1 << 16 ]
set AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR [expr 0x2 << 16 ]
set AT91C_MATRIX_FIXED_DEFMSTR3 [expr 0x7 << 18 ]
set AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I [expr 0x0 << 18 ]
set AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D [expr 0x1 << 18 ]
set AT91C_MATRIX_FIXED_DEFMSTR3_HPDC3 [expr 0x2 << 18 ]
set AT91C_MATRIX_FIXED_DEFMSTR3_LCDC [expr 0x3 << 18 ]
set AT91C_MATRIX_FIXED_DEFMSTR3_DMA [expr 0x4 << 18 ]
# -------- MATRIX_SCFG4 : (MATRIX Offset: 0x50) Slave Configuration Register 4 --------
set AT91C_MATRIX_SLOT_CYCLE [expr 0xFF << 0 ]
set AT91C_MATRIX_DEFMSTR_TYPE [expr 0x3 << 16 ]
set AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR [expr 0x0 << 16 ]
set AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR [expr 0x1 << 16 ]
set AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR [expr 0x2 << 16 ]
set AT91C_MATRIX_FIXED_DEFMSTR4 [expr 0x3 << 18 ]
set AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I [expr 0x0 << 18 ]
set AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D [expr 0x1 << 18 ]
set AT91C_MATRIX_FIXED_DEFMSTR4_HPDC3 [expr 0x2 << 18 ]
# -------- MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register --------
set AT91C_MATRIX_RCA926I [expr 0x1 << 0 ]
set AT91C_MATRIX_RCA926D [expr 0x1 << 1 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Chip Configuration Registers
# *****************************************************************************
# -------- CCFG_EBICSA : (CCFG Offset: 0xc) EBI Chip Select Assignement Register --------
set AT91C_EBI_CS1A [expr 0x1 << 1 ]
set AT91C_EBI_CS1A_SMC [expr 0x0 << 1 ]
set AT91C_EBI_CS1A_SDRAMC [expr 0x1 << 1 ]
set AT91C_EBI_CS3A [expr 0x1 << 3 ]
set AT91C_EBI_CS3A_SMC [expr 0x0 << 3 ]
set AT91C_EBI_CS3A_SM [expr 0x1 << 3 ]
set AT91C_EBI_CS4A [expr 0x1 << 4 ]
set AT91C_EBI_CS4A_SMC [expr 0x0 << 4 ]
set AT91C_EBI_CS4A_CF [expr 0x1 << 4 ]
set AT91C_EBI_CS5A [expr 0x1 << 5 ]
set AT91C_EBI_CS5A_SMC [expr 0x0 << 5 ]
set AT91C_EBI_CS5A_CF [expr 0x1 << 5 ]
set AT91C_EBI_DBPUC [expr 0x1 << 8 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Peripheral DMA Controller
# *****************************************************************************
# -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
set AT91C_PDC_RXTEN [expr 0x1 << 0 ]
set AT91C_PDC_RXTDIS [expr 0x1 << 1 ]
set AT91C_PDC_TXTEN [expr 0x1 << 8 ]
set AT91C_PDC_TXTDIS [expr 0x1 << 9 ]
# -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
set AT91C_PDC_RXTEN [expr 0x1 << 0 ]
set AT91C_PDC_TXTEN [expr 0x1 << 8 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Debug Unit
# *****************************************************************************
# -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
set AT91C_US_RSTRX [expr 0x1 << 2 ]
set AT91C_US_RSTTX [expr 0x1 << 3 ]
set AT91C_US_RXEN [expr 0x1 << 4 ]
set AT91C_US_RXDIS [expr 0x1 << 5 ]
set AT91C_US_TXEN [expr 0x1 << 6 ]
set AT91C_US_TXDIS [expr 0x1 << 7 ]
set AT91C_US_RSTSTA [expr 0x1 << 8 ]
# -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
set AT91C_US_PAR [expr 0x7 << 9 ]
set AT91C_US_PAR_EVEN [expr 0x0 << 9 ]
set AT91C_US_PAR_ODD [expr 0x1 << 9 ]
set AT91C_US_PAR_SPACE [expr 0x2 << 9 ]
set AT91C_US_PAR_MARK [expr 0x3 << 9 ]
set AT91C_US_PAR_NONE [expr 0x4 << 9 ]
set AT91C_US_PAR_MULTI_DROP [expr 0x6 << 9 ]
set AT91C_US_CHMODE [expr 0x3 << 14 ]
set AT91C_US_CHMODE_NORMAL [expr 0x0 << 14 ]
set AT91C_US_CHMODE_AUTO [expr 0x1 << 14 ]
set AT91C_US_CHMODE_LOCAL [expr 0x2 << 14 ]
set AT91C_US_CHMODE_REMOTE [expr 0x3 << 14 ]
# -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
set AT91C_US_RXRDY [expr 0x1 << 0 ]
set AT91C_US_TXRDY [expr 0x1 << 1 ]
set AT91C_US_ENDRX [expr 0x1 << 3 ]
set AT91C_US_ENDTX [expr 0x1 << 4 ]
set AT91C_US_OVRE [expr 0x1 << 5 ]
set AT91C_US_FRAME [expr 0x1 << 6 ]
set AT91C_US_PARE [expr 0x1 << 7 ]
set AT91C_US_TXEMPTY [expr 0x1 << 9 ]
set AT91C_US_TXBUFE [expr 0x1 << 11 ]
set AT91C_US_RXBUFF [expr 0x1 << 12 ]
set AT91C_US_COMM_TX [expr 0x1 << 30 ]
set AT91C_US_COMM_RX [expr 0x1 << 31 ]
# -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
set AT91C_US_RXRDY [expr 0x1 << 0 ]
set AT91C_US_TXRDY [expr 0x1 << 1 ]
set AT91C_US_ENDRX [expr 0x1 << 3 ]
set AT91C_US_ENDTX [expr 0x1 << 4 ]
set AT91C_US_OVRE [expr 0x1 << 5 ]
set AT91C_US_FRAME [expr 0x1 << 6 ]
set AT91C_US_PARE [expr 0x1 << 7 ]
set AT91C_US_TXEMPTY [expr 0x1 << 9 ]
set AT91C_US_TXBUFE [expr 0x1 << 11 ]
set AT91C_US_RXBUFF [expr 0x1 << 12 ]
set AT91C_US_COMM_TX [expr 0x1 << 30 ]
set AT91C_US_COMM_RX [expr 0x1 << 31 ]
# -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
set AT91C_US_RXRDY [expr 0x1 << 0 ]
set AT91C_US_TXRDY [expr 0x1 << 1 ]
set AT91C_US_ENDRX [expr 0x1 << 3 ]
set AT91C_US_ENDTX [expr 0x1 << 4 ]
set AT91C_US_OVRE [expr 0x1 << 5 ]
set AT91C_US_FRAME [expr 0x1 << 6 ]
set AT91C_US_PARE [expr 0x1 << 7 ]
set AT91C_US_TXEMPTY [expr 0x1 << 9 ]
set AT91C_US_TXBUFE [expr 0x1 << 11 ]
set AT91C_US_RXBUFF [expr 0x1 << 12 ]
set AT91C_US_COMM_TX [expr 0x1 << 30 ]
set AT91C_US_COMM_RX [expr 0x1 << 31 ]
# -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
set AT91C_US_RXRDY [expr 0x1 << 0 ]
set AT91C_US_TXRDY [expr 0x1 << 1 ]
set AT91C_US_ENDRX [expr 0x1 << 3 ]
set AT91C_US_ENDTX [expr 0x1 << 4 ]
set AT91C_US_OVRE [expr 0x1 << 5 ]
set AT91C_US_FRAME [expr 0x1 << 6 ]
set AT91C_US_PARE [expr 0x1 << 7 ]
set AT91C_US_TXEMPTY [expr 0x1 << 9 ]
set AT91C_US_TXBUFE [expr 0x1 << 11 ]
set AT91C_US_RXBUFF [expr 0x1 << 12 ]
set AT91C_US_COMM_TX [expr 0x1 << 30 ]
set AT91C_US_COMM_RX [expr 0x1 << 31 ]
# -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
set AT91C_US_FORCE_NTRST [expr 0x1 << 0 ]
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