?? at91sam9260.tcl
字號(hào):
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
# *****************************************************************************
# -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
set AT91C_AIC_PRIOR [expr 0x7 << 0 ]
set AT91C_AIC_PRIOR_LOWEST 0x0
set AT91C_AIC_PRIOR_HIGHEST 0x7
set AT91C_AIC_SRCTYPE [expr 0x3 << 5 ]
set AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE [expr 0x0 << 5 ]
set AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED [expr 0x1 << 5 ]
set AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL [expr 0x2 << 5 ]
set AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE [expr 0x3 << 5 ]
# -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
set AT91C_AIC_NFIQ [expr 0x1 << 0 ]
set AT91C_AIC_NIRQ [expr 0x1 << 1 ]
# -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
set AT91C_AIC_DCR_PROT [expr 0x1 << 0 ]
set AT91C_AIC_DCR_GMSK [expr 0x1 << 1 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Parallel Input Output Controler
# *****************************************************************************
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Clock Generator Controler
# *****************************************************************************
# -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
set AT91C_CKGR_MOSCEN [expr 0x1 << 0 ]
set AT91C_CKGR_OSCBYPASS [expr 0x1 << 1 ]
set AT91C_CKGR_OSCOUNT [expr 0xFF << 8 ]
# -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
set AT91C_CKGR_MAINF [expr 0xFFFF << 0 ]
set AT91C_CKGR_MAINRDY [expr 0x1 << 16 ]
# -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register --------
set AT91C_CKGR_DIVA [expr 0xFF << 0 ]
set AT91C_CKGR_DIVA_0 0x0
set AT91C_CKGR_DIVA_BYPASS 0x1
set AT91C_CKGR_PLLACOUNT [expr 0x3F << 8 ]
set AT91C_CKGR_OUTA [expr 0x3 << 14 ]
set AT91C_CKGR_OUTA_0 [expr 0x0 << 14 ]
set AT91C_CKGR_OUTA_1 [expr 0x1 << 14 ]
set AT91C_CKGR_OUTA_2 [expr 0x2 << 14 ]
set AT91C_CKGR_OUTA_3 [expr 0x3 << 14 ]
set AT91C_CKGR_MULA [expr 0x7FF << 16 ]
set AT91C_CKGR_SRCA [expr 0x1 << 29 ]
# -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register --------
set AT91C_CKGR_DIVB [expr 0xFF << 0 ]
set AT91C_CKGR_DIVB_0 0x0
set AT91C_CKGR_DIVB_BYPASS 0x1
set AT91C_CKGR_PLLBCOUNT [expr 0x3F << 8 ]
set AT91C_CKGR_OUTB [expr 0x3 << 14 ]
set AT91C_CKGR_OUTB_0 [expr 0x0 << 14 ]
set AT91C_CKGR_OUTB_1 [expr 0x1 << 14 ]
set AT91C_CKGR_OUTB_2 [expr 0x2 << 14 ]
set AT91C_CKGR_OUTB_3 [expr 0x3 << 14 ]
set AT91C_CKGR_MULB [expr 0x7FF << 16 ]
set AT91C_CKGR_USBDIV [expr 0x3 << 28 ]
set AT91C_CKGR_USBDIV_0 [expr 0x0 << 28 ]
set AT91C_CKGR_USBDIV_1 [expr 0x1 << 28 ]
set AT91C_CKGR_USBDIV_2 [expr 0x2 << 28 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Power Management Controler
# *****************************************************************************
# -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
set AT91C_PMC_PCK [expr 0x1 << 0 ]
set AT91C_PMC_UHP [expr 0x1 << 6 ]
set AT91C_PMC_UDP [expr 0x1 << 7 ]
set AT91C_PMC_PCK0 [expr 0x1 << 8 ]
set AT91C_PMC_PCK1 [expr 0x1 << 9 ]
set AT91C_PMC_HCK0 [expr 0x1 << 16 ]
set AT91C_PMC_HCK1 [expr 0x1 << 17 ]
# -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
set AT91C_PMC_PCK [expr 0x1 << 0 ]
set AT91C_PMC_UHP [expr 0x1 << 6 ]
set AT91C_PMC_UDP [expr 0x1 << 7 ]
set AT91C_PMC_PCK0 [expr 0x1 << 8 ]
set AT91C_PMC_PCK1 [expr 0x1 << 9 ]
set AT91C_PMC_HCK0 [expr 0x1 << 16 ]
set AT91C_PMC_HCK1 [expr 0x1 << 17 ]
# -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
set AT91C_PMC_PCK [expr 0x1 << 0 ]
set AT91C_PMC_UHP [expr 0x1 << 6 ]
set AT91C_PMC_UDP [expr 0x1 << 7 ]
set AT91C_PMC_PCK0 [expr 0x1 << 8 ]
set AT91C_PMC_PCK1 [expr 0x1 << 9 ]
set AT91C_PMC_HCK0 [expr 0x1 << 16 ]
set AT91C_PMC_HCK1 [expr 0x1 << 17 ]
# -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
set AT91C_CKGR_MOSCEN [expr 0x1 << 0 ]
set AT91C_CKGR_OSCBYPASS [expr 0x1 << 1 ]
set AT91C_CKGR_OSCOUNT [expr 0xFF << 8 ]
# -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
set AT91C_CKGR_MAINF [expr 0xFFFF << 0 ]
set AT91C_CKGR_MAINRDY [expr 0x1 << 16 ]
# -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register --------
set AT91C_CKGR_DIVA [expr 0xFF << 0 ]
set AT91C_CKGR_DIVA_0 0x0
set AT91C_CKGR_DIVA_BYPASS 0x1
set AT91C_CKGR_PLLACOUNT [expr 0x3F << 8 ]
set AT91C_CKGR_OUTA [expr 0x3 << 14 ]
set AT91C_CKGR_OUTA_0 [expr 0x0 << 14 ]
set AT91C_CKGR_OUTA_1 [expr 0x1 << 14 ]
set AT91C_CKGR_OUTA_2 [expr 0x2 << 14 ]
set AT91C_CKGR_OUTA_3 [expr 0x3 << 14 ]
set AT91C_CKGR_MULA [expr 0x7FF << 16 ]
set AT91C_CKGR_SRCA [expr 0x1 << 29 ]
# -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register --------
set AT91C_CKGR_DIVB [expr 0xFF << 0 ]
set AT91C_CKGR_DIVB_0 0x0
set AT91C_CKGR_DIVB_BYPASS 0x1
set AT91C_CKGR_PLLBCOUNT [expr 0x3F << 8 ]
set AT91C_CKGR_OUTB [expr 0x3 << 14 ]
set AT91C_CKGR_OUTB_0 [expr 0x0 << 14 ]
set AT91C_CKGR_OUTB_1 [expr 0x1 << 14 ]
set AT91C_CKGR_OUTB_2 [expr 0x2 << 14 ]
set AT91C_CKGR_OUTB_3 [expr 0x3 << 14 ]
set AT91C_CKGR_MULB [expr 0x7FF << 16 ]
set AT91C_CKGR_USBDIV [expr 0x3 << 28 ]
set AT91C_CKGR_USBDIV_0 [expr 0x0 << 28 ]
set AT91C_CKGR_USBDIV_1 [expr 0x1 << 28 ]
set AT91C_CKGR_USBDIV_2 [expr 0x2 << 28 ]
# -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
set AT91C_PMC_CSS [expr 0x3 << 0 ]
set AT91C_PMC_CSS_SLOW_CLK 0x0
set AT91C_PMC_CSS_MAIN_CLK 0x1
set AT91C_PMC_CSS_PLLA_CLK 0x2
set AT91C_PMC_CSS_PLLB_CLK 0x3
set AT91C_PMC_PRES [expr 0x7 << 2 ]
set AT91C_PMC_PRES_CLK [expr 0x0 << 2 ]
set AT91C_PMC_PRES_CLK_2 [expr 0x1 << 2 ]
set AT91C_PMC_PRES_CLK_4 [expr 0x2 << 2 ]
set AT91C_PMC_PRES_CLK_8 [expr 0x3 << 2 ]
set AT91C_PMC_PRES_CLK_16 [expr 0x4 << 2 ]
set AT91C_PMC_PRES_CLK_32 [expr 0x5 << 2 ]
set AT91C_PMC_PRES_CLK_64 [expr 0x6 << 2 ]
set AT91C_PMC_MDIV [expr 0x3 << 8 ]
set AT91C_PMC_MDIV_1 [expr 0x0 << 8 ]
set AT91C_PMC_MDIV_2 [expr 0x1 << 8 ]
set AT91C_PMC_MDIV_3 [expr 0x2 << 8 ]
# -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
set AT91C_PMC_CSS [expr 0x3 << 0 ]
set AT91C_PMC_CSS_SLOW_CLK 0x0
set AT91C_PMC_CSS_MAIN_CLK 0x1
set AT91C_PMC_CSS_PLLA_CLK 0x2
set AT91C_PMC_CSS_PLLB_CLK 0x3
set AT91C_PMC_PRES [expr 0x7 << 2 ]
set AT91C_PMC_PRES_CLK [expr 0x0 << 2 ]
set AT91C_PMC_PRES_CLK_2 [expr 0x1 << 2 ]
set AT91C_PMC_PRES_CLK_4 [expr 0x2 << 2 ]
set AT91C_PMC_PRES_CLK_8 [expr 0x3 << 2 ]
set AT91C_PMC_PRES_CLK_16 [expr 0x4 << 2 ]
set AT91C_PMC_PRES_CLK_32 [expr 0x5 << 2 ]
set AT91C_PMC_PRES_CLK_64 [expr 0x6 << 2 ]
# -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
set AT91C_PMC_MOSCS [expr 0x1 << 0 ]
set AT91C_PMC_LOCKA [expr 0x1 << 1 ]
set AT91C_PMC_LOCKB [expr 0x1 << 2 ]
set AT91C_PMC_MCKRDY [expr 0x1 << 3 ]
set AT91C_PMC_PCK0RDY [expr 0x1 << 8 ]
set AT91C_PMC_PCK1RDY [expr 0x1 << 9 ]
# -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
set AT91C_PMC_MOSCS [expr 0x1 << 0 ]
set AT91C_PMC_LOCKA [expr 0x1 << 1 ]
set AT91C_PMC_LOCKB [expr 0x1 << 2 ]
set AT91C_PMC_MCKRDY [expr 0x1 << 3 ]
set AT91C_PMC_PCK0RDY [expr 0x1 << 8 ]
set AT91C_PMC_PCK1RDY [expr 0x1 << 9 ]
# -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
set AT91C_PMC_MOSCS [expr 0x1 << 0 ]
set AT91C_PMC_LOCKA [expr 0x1 << 1 ]
set AT91C_PMC_LOCKB [expr 0x1 << 2 ]
set AT91C_PMC_MCKRDY [expr 0x1 << 3 ]
set AT91C_PMC_PCK0RDY [expr 0x1 << 8 ]
set AT91C_PMC_PCK1RDY [expr 0x1 << 9 ]
# -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
set AT91C_PMC_MOSCS [expr 0x1 << 0 ]
set AT91C_PMC_LOCKA [expr 0x1 << 1 ]
set AT91C_PMC_LOCKB [expr 0x1 << 2 ]
set AT91C_PMC_MCKRDY [expr 0x1 << 3 ]
set AT91C_PMC_PCK0RDY [expr 0x1 << 8 ]
set AT91C_PMC_PCK1RDY [expr 0x1 << 9 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Reset Controller Interface
# *****************************************************************************
# -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
set AT91C_RSTC_PROCRST [expr 0x1 << 0 ]
set AT91C_RSTC_ICERST [expr 0x1 << 1 ]
set AT91C_RSTC_PERRST [expr 0x1 << 2 ]
set AT91C_RSTC_EXTRST [expr 0x1 << 3 ]
set AT91C_RSTC_KEY [expr 0xFF << 24 ]
# -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
set AT91C_RSTC_URSTS [expr 0x1 << 0 ]
set AT91C_RSTC_RSTTYP [expr 0x7 << 8 ]
set AT91C_RSTC_RSTTYP_GENERAL [expr 0x0 << 8 ]
set AT91C_RSTC_RSTTYP_WAKEUP [expr 0x1 << 8 ]
set AT91C_RSTC_RSTTYP_WATCHDOG [expr 0x2 << 8 ]
set AT91C_RSTC_RSTTYP_SOFTWARE [expr 0x3 << 8 ]
set AT91C_RSTC_RSTTYP_USER [expr 0x4 << 8 ]
set AT91C_RSTC_NRSTL [expr 0x1 << 16 ]
set AT91C_RSTC_SRCMP [expr 0x1 << 17 ]
# -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
set AT91C_RSTC_URSTEN [expr 0x1 << 0 ]
set AT91C_RSTC_URSTIEN [expr 0x1 << 4 ]
set AT91C_RSTC_ERSTL [expr 0xF << 8 ]
set AT91C_RSTC_KEY [expr 0xFF << 24 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Shut Down Controller Interface
# *****************************************************************************
# -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register --------
set AT91C_SHDWC_SHDW [expr 0x1 << 0 ]
set AT91C_SHDWC_KEY [expr 0xFF << 24 ]
# -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register --------
set AT91C_SHDWC_WKMODE0 [expr 0x3 << 0 ]
set AT91C_SHDWC_WKMODE0_NONE 0x0
set AT91C_SHDWC_WKMODE0_HIGH 0x1
set AT91C_SHDWC_WKMODE0_LOW 0x2
set AT91C_SHDWC_WKMODE0_ANYLEVEL 0x3
set AT91C_SHDWC_CPTWK0 [expr 0xF << 4 ]
set AT91C_SHDWC_WKMODE1 [expr 0x3 << 8 ]
set AT91C_SHDWC_WKMODE1_NONE [expr 0x0 << 8 ]
set AT91C_SHDWC_WKMODE1_HIGH [expr 0x1 << 8 ]
set AT91C_SHDWC_WKMODE1_LOW [expr 0x2 << 8 ]
set AT91C_SHDWC_WKMODE1_ANYLEVEL [expr 0x3 << 8 ]
set AT91C_SHDWC_CPTWK1 [expr 0xF << 12 ]
set AT91C_SHDWC_RTTWKEN [expr 0x1 << 16 ]
set AT91C_SHDWC_RTCWKEN [expr 0x1 << 17 ]
# -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register --------
set AT91C_SHDWC_WAKEUP0 [expr 0x1 << 0 ]
set AT91C_SHDWC_WAKEUP1 [expr 0x1 << 1 ]
set AT91C_SHDWC_FWKUP [expr 0x1 << 2 ]
set AT91C_SHDWC_RTTWK [expr 0x1 << 16 ]
?? 快捷鍵說(shuō)明
復(fù)制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號(hào)
Ctrl + =
減小字號(hào)
Ctrl + -