?? at91sam9260_adc.h
字號:
#define AT91C_ADC_CH0 (0x1 << 0 ) /**< (ADC) Channel 0 */
#define AT91C_ADC_CH1 (0x1 << 1 ) /**< (ADC) Channel 1 */
#define AT91C_ADC_CH2 (0x1 << 2 ) /**< (ADC) Channel 2 */
#define AT91C_ADC_CH3 (0x1 << 3 ) /**< (ADC) Channel 3 */
#define AT91C_ADC_CH4 (0x1 << 4 ) /**< (ADC) Channel 4 */
#define AT91C_ADC_CH5 (0x1 << 5 ) /**< (ADC) Channel 5 */
#define AT91C_ADC_CH6 (0x1 << 6 ) /**< (ADC) Channel 6 */
#define AT91C_ADC_CH7 (0x1 << 7 ) /**< (ADC) Channel 7 */
/* --- Register ADC_CHSR */
#define AT91C_ADC_CH0 (0x1 << 0 ) /**< (ADC) Channel 0 */
#define AT91C_ADC_CH1 (0x1 << 1 ) /**< (ADC) Channel 1 */
#define AT91C_ADC_CH2 (0x1 << 2 ) /**< (ADC) Channel 2 */
#define AT91C_ADC_CH3 (0x1 << 3 ) /**< (ADC) Channel 3 */
#define AT91C_ADC_CH4 (0x1 << 4 ) /**< (ADC) Channel 4 */
#define AT91C_ADC_CH5 (0x1 << 5 ) /**< (ADC) Channel 5 */
#define AT91C_ADC_CH6 (0x1 << 6 ) /**< (ADC) Channel 6 */
#define AT91C_ADC_CH7 (0x1 << 7 ) /**< (ADC) Channel 7 */
/* --- Register ADC_SR */
#define AT91C_ADC_EOC0 (0x1 << 0 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC1 (0x1 << 1 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC2 (0x1 << 2 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC3 (0x1 << 3 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC4 (0x1 << 4 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC5 (0x1 << 5 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC6 (0x1 << 6 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC7 (0x1 << 7 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_OVRE0 (0x1 << 8 ) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE1 (0x1 << 9 ) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE2 (0x1 << 10) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE3 (0x1 << 11) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE4 (0x1 << 12) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE5 (0x1 << 13) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE6 (0x1 << 14) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE7 (0x1 << 15) /**< (ADC) Overrun Error */
#define AT91C_ADC_DRDY (0x1 << 16) /**< (ADC) Data Ready */
#define AT91C_ADC_GOVRE (0x1 << 17) /**< (ADC) General Overrun */
#define AT91C_ADC_ENDRX (0x1 << 18) /**< (ADC) End of Receiver Transfer */
#define AT91C_ADC_RXBUFF (0x1 << 19) /**< (ADC) RXBUFF Interrupt */
/* --- Register ADC_LCDR */
#define AT91C_ADC_LDATA (0x3FF << 0 ) /**< (ADC) Last Data Converted */
/* --- Register ADC_IER */
#define AT91C_ADC_EOC0 (0x1 << 0 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC1 (0x1 << 1 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC2 (0x1 << 2 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC3 (0x1 << 3 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC4 (0x1 << 4 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC5 (0x1 << 5 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC6 (0x1 << 6 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC7 (0x1 << 7 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_OVRE0 (0x1 << 8 ) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE1 (0x1 << 9 ) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE2 (0x1 << 10) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE3 (0x1 << 11) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE4 (0x1 << 12) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE5 (0x1 << 13) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE6 (0x1 << 14) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE7 (0x1 << 15) /**< (ADC) Overrun Error */
#define AT91C_ADC_DRDY (0x1 << 16) /**< (ADC) Data Ready */
#define AT91C_ADC_GOVRE (0x1 << 17) /**< (ADC) General Overrun */
#define AT91C_ADC_ENDRX (0x1 << 18) /**< (ADC) End of Receiver Transfer */
#define AT91C_ADC_RXBUFF (0x1 << 19) /**< (ADC) RXBUFF Interrupt */
/* --- Register ADC_IDR */
#define AT91C_ADC_EOC0 (0x1 << 0 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC1 (0x1 << 1 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC2 (0x1 << 2 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC3 (0x1 << 3 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC4 (0x1 << 4 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC5 (0x1 << 5 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC6 (0x1 << 6 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC7 (0x1 << 7 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_OVRE0 (0x1 << 8 ) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE1 (0x1 << 9 ) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE2 (0x1 << 10) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE3 (0x1 << 11) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE4 (0x1 << 12) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE5 (0x1 << 13) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE6 (0x1 << 14) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE7 (0x1 << 15) /**< (ADC) Overrun Error */
#define AT91C_ADC_DRDY (0x1 << 16) /**< (ADC) Data Ready */
#define AT91C_ADC_GOVRE (0x1 << 17) /**< (ADC) General Overrun */
#define AT91C_ADC_ENDRX (0x1 << 18) /**< (ADC) End of Receiver Transfer */
#define AT91C_ADC_RXBUFF (0x1 << 19) /**< (ADC) RXBUFF Interrupt */
/* --- Register ADC_IMR */
#define AT91C_ADC_EOC0 (0x1 << 0 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC1 (0x1 << 1 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC2 (0x1 << 2 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC3 (0x1 << 3 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC4 (0x1 << 4 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC5 (0x1 << 5 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC6 (0x1 << 6 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_EOC7 (0x1 << 7 ) /**< (ADC) End of Conversion */
#define AT91C_ADC_OVRE0 (0x1 << 8 ) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE1 (0x1 << 9 ) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE2 (0x1 << 10) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE3 (0x1 << 11) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE4 (0x1 << 12) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE5 (0x1 << 13) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE6 (0x1 << 14) /**< (ADC) Overrun Error */
#define AT91C_ADC_OVRE7 (0x1 << 15) /**< (ADC) Overrun Error */
#define AT91C_ADC_DRDY (0x1 << 16) /**< (ADC) Data Ready */
#define AT91C_ADC_GOVRE (0x1 << 17) /**< (ADC) General Overrun */
#define AT91C_ADC_ENDRX (0x1 << 18) /**< (ADC) End of Receiver Transfer */
#define AT91C_ADC_RXBUFF (0x1 << 19) /**< (ADC) RXBUFF Interrupt */
/* --- Register ADC_CDR0 */
#define AT91C_ADC_DATA (0x3FF << 0 ) /**< (ADC) Converted Data */
/* --- Register ADC_CDR1 */
#define AT91C_ADC_DATA (0x3FF << 0 ) /**< (ADC) Converted Data */
/* --- Register ADC_CDR2 */
#define AT91C_ADC_DATA (0x3FF << 0 ) /**< (ADC) Converted Data */
/* --- Register ADC_CDR3 */
#define AT91C_ADC_DATA (0x3FF << 0 ) /**< (ADC) Converted Data */
/* --- Register ADC_CDR4 */
#define AT91C_ADC_DATA (0x3FF << 0 ) /**< (ADC) Converted Data */
/* --- Register ADC_CDR5 */
#define AT91C_ADC_DATA (0x3FF << 0 ) /**< (ADC) Converted Data */
/* --- Register ADC_CDR6 */
#define AT91C_ADC_DATA (0x3FF << 0 ) /**< (ADC) Converted Data */
/* --- Register ADC_CDR7 */
#define AT91C_ADC_DATA (0x3FF << 0 ) /**< (ADC) Converted Data */
#endif /* __AT91SAM9260_ADC_H */
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