?? cdr14iic.c
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struct{ u8 u8_IdxActJob; // index to first Job (active, if NumOfJobs>0) u8 u8_NumOfJobs; // number of scheduled jobs 0..DR14_MAX_JOBS-1 u8 u8_ErrorCount; // jobs are restarted until error count is 0 u8 u8_NextTrf; // counts transfers of active job (for restart) u8 u8_StopRequested; u8 u8_Busy; // num of jobs > 0 u8 u8_Abort; // controls p_dr14_IICEndOfJob u8 u8_Sta; // sys2_IIC.sta (reason for abort) u8 u8_Dackn; // 0..SYS2_GPIO_MAX, or disabled if >SYS2_GPIO_MAX u8 u8_Clk; // 0x00, 0x01, 0x02, 0x03 = 36, 48, 72, 96 kHz u8 filler[2]; u8 * pu8_Result; // result in case of DR04_IIC_RESULT t_dr04_IICJob st_ActTrf; // current transfer of active job const t_dr04_IICJob *pst_Jobs[DR14_MAX_JOBS]; // scheduled jobs u8 u8_Dev [DR14_MAX_JOBS];} st_dr14_IIC;//#######################################################################ifndef VegaPro /* Notes: * - we cannot write IIC_CON and check IIC_STA afterwards bec' it * is already changed * - SI must always be written as the last IIC register (in time) * - If START (IIC_STA) is to be written to IIC_CON, we have to check * whether the IIC is already active (u8_Status != DR14_IIC_F8_SIO_BUSY). * If so, then SI be written to start the IIC activity. If the IIC * bus is idle it MUST not be written, because this would cause a * a second activation of the IIC bus which cause failures in the IIC * handler when the first activity was already completed by then. */INLINE void p_dr14_SetControl(u32 conVal){ // to INLINE or not to INLINE: +12bytes of ROM for INLINE (but saves some cycles) DR14_IIC_DUMP(DUMP_STA,u8_Status); if((conVal) & DR14_IIC_STP) { VOLAT_U16(sys2_IIC.sto)= 1; } VOLATILE(sys2_IIC.con,u16)= (conVal); if ((conVal & DR14_IIC_STA) == 0 || !st_dr14_IIC.u8_StopRequested) { DR14_IIC_DUMP(DUMP_MARK,0xE5); VOLATILE(sys2_IIC.si,u16) = 0; } if((conVal) & DR14_IIC_STP) { st_dr14_IIC.u8_StopRequested= 1; } DR14_IIC_DUMP(DUMP_CON,(conVal));}#else // for VegaPro#define p_dr14_SetControl(conVal)\ VOLATILE(sys2_IIC.con,u16)= (conVal);DR14_IIC_DUMP(DUMP_CON,conVal)#endif // Vega?/* FUNCTIONAL DESCRIPTION * * Provides a synchronized version of p_dr14_IICSchedule so: * - buffers need not to be global or static * - buffers can be reused immediately after the function returns * * Nevertheless it should be used with caution because synchronization * implies an active wait loop, so calling it from interrupt level * is forbidden and calling from process level needs special * justification. * * PARAMETER * u8_Slave address of the device on the IIC bus (without R/W bit) * firstJob points to first single job of transmission to perform * * INTERFACE DECLARATION: ****************************************************/void p_dr14_IICTransmit(u8 u8_Slave, const t_dr04_IICJob *pst_FirstJob){ while(VOLAT_U8(st_dr14_IIC.u8_Busy)); // only one p_dr14_IICTransmit in Queue p_dr14_IICSchedule(u8_Slave, pst_FirstJob); while(VOLAT_U8(st_dr14_IIC.u8_Busy)); // until all done (longer than nec)} /* p_dr14_IICTransmit *//* FUNCTIONAL DESCRIPTION * * This function transmits n bytes and waits for completion. * It takes a simple buffer and builds up the one step t_dr04_IICJob * internally. * * As it is just a wrapper for p_dr14_IICTransmit, the description * of that function applies as well. * * PARAMETER * u8_Slave device address on the IIC bus * u8_Ctrl (IIC_READ / IIC_WRITE) + address modifiers as afforded * pv_Buf buffer which contains the bytes to write * u8_NBytes number of bytes to write from buffer * returns 1 ok * else error state * * INTERFACE DECLARATION: ***************************************************/s32 p_dr14_IICImmediate(u8 u8_Slave, u8 u8_Ctrl, void *pv_Buf, u32 u8_NBytes){ t_dr04_IICJob st_ImmediateJob[3]; st_ImmediateJob[0].un_Ctrl= DR04_IIC_RESULT; st_ImmediateJob[0].un_NBytes= 0; st_ImmediateJob[0].pu8_Buf= &st_ImmediateJob[0].un_NBytes; st_ImmediateJob[1].un_Ctrl= u8_Ctrl; st_ImmediateJob[1].un_NBytes= u8_NBytes; st_ImmediateJob[1].pu8_Buf= pv_Buf; st_ImmediateJob[2].un_Ctrl= DR04_IIC_END_OF_JOBS; p_dr14_IICTransmit(u8_Slave, st_ImmediateJob); return st_ImmediateJob[0].un_NBytes;} /* p_dr14_IICImmediate */#if 0 /* the following only for documentation pruposes *//* FUNCTIONAL DESCRIPTION: * * This macro implements a synchronous write operation * using p_dr14_IICImmediate. * * IIC_WRITE is used as un_Ctrl byte without modifiers. * * PARAMETERS: * u8_Slave device address on the IIC bus to write to * pu8_Buffer buffer which contains the bytes to write * n number of bytes to write from buffer * * INTERFACE DECLARATION: ***************************************************/p_dr14_IICWrite(/*u8*/ u8_Slave, /*u8* */ pu8_Buffer, /*u8*/ u8_N){macro pseudo definition}/* FUNCTIONAL DESCRIPTION: * * This macro implements a synchronous read operation * using p_dr14_IICImmediate. * * IIC_READ is used as un_Ctrl byte without modifiers. * * PARAMETERS: * u8_Slave device address on the IIC bus to read from * pu8_Buffer buffer to accept the bytes from u8_Slave * n number of bytes to read into pu8_Buffer * * INTERFACE DECLARATION: ***************************************************/p_dr14_IICRead(/*u8*/ u8_Slave, /*u8* */ pu8_Buffer, /*u8*/ u8_N){macro pseudo definition}/* FUNCTIONAL DESCRIPTION: * * This macro returns the current state of the driver * * PARAMETERS: * return TRUE if transmissions in progress * * INTERFACE DECLARATION: ***************************************************/DR04_IIC_IS_BUSY{macro pseudo definition}/* FUNCTIONAL DESCRIPTION: * * This macro returns the current state of the driver * * PARAMETERS: * return TRUE if no transmission in progress * * INTERFACE DECLARATION: ***************************************************/DR04_IIC_IS_FREE{macro pseudo definition}#endif/* FUNCTIONAL DESCRIPTION * * Checks and handles the following conditions: * 1. if another job within the current transmission is to start or * 2. if another transmission is to initiate or * 3. if the iic bus is free again * * It also handles the IIC_EXECUTE control. If this control is found, * the address which indicates the transfer buffer in case of the * IIC_READ and IIC_WRITE controls, is interpreted as the address of * a function f(x) which has one parameter of type u8. The 'length' x * of the 'transfer buffer' is used to call f(x). As f(x) may be called * from IIC interupt and from program level as well, it has to be reentrant. * Further it should only introduce a minmum delay. * * INTERFACE DECLARATION: ***************************************************/void p_dr14_IICEndOfJob(void){ /* DESIGN * * Assumptions: * This function does not interrupt itself and nowhere else the queue * is modified, so no guard is needed, because: * i) if it is called from interrupt, it can not interrupt itself * ii) otherwise it is guarded as critical section in p_dr14_IICSchedule * */# ifdef VegaPro static u8 u8_CondStop;# endif /* loop through the jobs starting with the next */ for(;;) { if(st_dr14_IIC.u8_NextTrf++) { st_dr14_IIC.pst_Jobs[st_dr14_IIC.u8_IdxActJob]++; // inc unless first } else { st_dr14_IIC.pu8_Result= 0; // reset to no result st_dr14_IIC.u8_Abort= 0; st_dr14_IIC.u8_Sta= 1; // preset: no error, success } st_dr14_IIC.st_ActTrf= *st_dr14_IIC.pst_Jobs[st_dr14_IIC.u8_IdxActJob]; if ((st_dr14_IIC.st_ActTrf.un_Ctrl == DR04_IIC_END_OF_JOBS) || (st_dr14_IIC.u8_Abort != 0 ) ) { /* stop current transmission */ DR14_IIC_DUMP(DUMP_MARK,0xEF); p_dr14_SetControl(DR14_IIC_STOP); DR14_IIC_DUMP(DUMP_GPIODAT1,sys2_GPIO.dat1); DR14_IIC_DUMP_STOP; DR14_IIC_CHECK_FREE; st_dr14_IIC.u8_ErrorCount= DR14_IIC_MAX_ERRORS; st_dr14_IIC.u8_NextTrf= 0; if (st_dr14_IIC.pu8_Result) { *st_dr14_IIC.pu8_Result= st_dr14_IIC.u8_Sta; } st_dr14_IIC.u8_IdxActJob++; st_dr14_IIC.u8_IdxActJob %= DR14_MAX_JOBS; st_dr14_IIC.u8_NumOfJobs--; if (st_dr14_IIC.u8_NumOfJobs == 0) { /* no more jobs to do */# ifdef VegaPro u8_CondStop= 0;# endif st_dr14_IIC.u8_Busy= 0; break; } } else if (st_dr14_IIC.st_ActTrf.un_Ctrl == DR04_IIC_EXECUTE) { ((t_dr04_IICExecute)st_dr14_IIC.st_ActTrf.pu8_Buf) (st_dr14_IIC.st_ActTrf.un_NBytes); } else if (st_dr14_IIC.st_ActTrf.un_Ctrl == DR04_IIC_RESULT) { st_dr14_IIC.pu8_Result= st_dr14_IIC.st_ActTrf.pu8_Buf; } else { /* start for next job * (it would be nice, if we could delay the STOP until * END_OF_JOBS, but there is at least one device, which * does not like it) */ /* ASSERT (st_dr14_IIC.st_ActTrf.un_NBytes != 0) */ if (st_dr14_IIC.st_ActTrf.un_Ctrl & DR04_IIC_READ) { DR14_IIC_DUMP(DUMP_MARK,0xE1);# ifndef VegaPro /* For VegaTB/XS/Lite no STP+STA required for repeated start */ p_dr14_SetControl(DR14_IIC_START);# else /* it's a READ: do not STOP preceeding WRITE */ p_dr14_SetControl(DR14_IIC_START | u8_CondStop); u8_CondStop= DR14_IIC_STP; /* each READ is terminated by STOP */# endif } else { DR14_IIC_DUMP(DUMP_MARK,0xE0);# ifndef VegaPro /* For VegaTB/XS/Lite no STP+STA required for repeated start */ p_dr14_SetControl(DR14_IIC_START);# else /* it's a WRITE: STOP any preceeding job */ p_dr14_SetControl(DR14_IIC_START | DR14_IIC_STP); u8_CondStop= 0;# endif /* but not this,a consecutive READ might follow */ } break; } }} /* p_dr14_IICEndOfJob *//* FUNCTIONAL DESCRIPTION * * Accepts a list of read or write jobs to be performed as a unit. * The request is appended to the queue st_dr04_IICCbBuf and the IIC bus is * started if necessary (DR04_IIC_IS_BUSY will become TRUE). * * Transmissions proceed asynchronously, not waiting for completion. * The caller has to supply global/static data or has to wait for completion, * i.e. until DR04_IIC_IS_BUSY becomes FALSE. * * Overflow of st_dr04_IICCbBuf will result in an exception. * * The first job must not be empty. * * PARAMETER * u8_Slave address of the device on the IIC bus (w/o R/W) * firstJob points to first single transmission to perform * * EXAMPLE * to read bytes 17..20 from EEPROM: * * u8 eepStartAddress= 17; * u8 eepReadBuffer[4]; * * t_dr04_IICJob eepReadJobs[3] ={ * {IIC_WRITE, 1, &eepStartAddress} * ,{IIC_READ, 4, eepReadBuffer } * ,{IIC_END_OF_JOBS,0,0} * }; * * void readEEPROM(void) * { * p_dr14_IICSchedule(IIC_SLAVE_EEP, eepReadJobs); * // now the jobs are scheduled and will be done sometime
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