?? startup.s
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;
; Copyright (c) Microsoft Corporation. All rights reserved.
;
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;
INCLUDE kxarm.h
INCLUDE armmacros.s
INCLUDE s3c2440a.inc
;-------------------------------------------------------------------------------
MemoryMap EQU 0x2a4
BANK_SIZE EQU 0x00100000 ; 1MB per bank in MemoryMap array
BANK_SHIFT EQU 20
; Define RAM space for the Page Tables:
;
PHYBASE EQU 0x30000000 ; physical start
PTs EQU 0x30010000 ; 1st level page table address (PHYBASE + 0x10000)
; save room for interrupt vectors.
; Define MSP type
GBLA MSP_VER
MSP_VER SETA 1 ; 1(MSP1,2), 3(MSP3)
;-------------------------------------------------------------------------------
TEXTAREA
IMPORT main
; Set up the MMU and Dcache for bootloader.
;
; This routine will initialize the first-level page table based up the contents
; of the MemoryMap array and enable the MMU and caches.
;
; Copy the image to RAM if it's not already running there.
;
; Include Files
; Defines
;------------------------------------------------------------------------------
; BUGBUG - ?
PLLVAL EQU (((0x61 << 12) + (0x1 << 4) + 0x2)) ;//c ksk 20051111
;------------------------------------------------------------------------------
; Cache Configuration
DCACHE_LINES_PER_SET_BITS EQU (6)
DCACHE_LINES_PER_SET EQU (64)
DCACHE_NUM_SETS EQU (8)
DCACHE_SET_INDEX_BIT EQU (32 - DCACHE_LINES_PER_SET_BITS)
DCACHE_LINE_SIZE EQU (32)
; External Variables
; External Functions
; Global Variables
; Local Variables
; Local Functions
;-------------------------------------------------------------------------------
; Function: Startup
;
; Main entry point for CPU initialization.
;
STARTUPTEXT
LEAF_ENTRY StartUp
; Jump over power-off code.
b ResetHandler
ResetHandler
; Make sure that TLB & cache are consistent
mov r0, #0
mcr p15, 0, r0, c8, c7, 0 ; flush both TLB
mcr p15, 0, r0, c7, c5, 0 ; invalidate instruction cache
mcr p15, 0, r0, c7, c6, 0 ; invalidate data cache
ldr r0, = GPFCON
ldr r1, = 0x55aa
str r1, [r0]
ldr r0, = WTCON ; disable watch dog
ldr r1, = 0x0
str r1, [r0]
ldr r0, = INTMSK
ldr r1, = 0xffffffff ; disable all interrupts
str r1, [r0]
ldr r0, = INTSUBMSK
ldr r1, = 0x7fff ; disable all sub interrupt
str r1, [r0]
ldr r0, = INTMOD
mov r1, #0x0 ; set all interrupt as IRQ
str r1, [r0]
ldr r0, = CLKDIVN
ldr r1, = 0x7 ; 0x0 = 1:1:1, 0x1 = 1:1:2, 0x2 = 1:2:2, 0x3 = 1:2:4,
; 0x7 = 1:3:6, 0x8 = 1:4:4
str r1, [r0]
ands r1, r1, #0xe ; set AsyncBusMode
beq %F10
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #R1_nF:OR:R1_iA
mcr p15, 0, r0, c1, c0, 0
10
ldr r0, = LOCKTIME ; To reduce PLL lock time, adjust the LOCKTIME register.
ldr r1, = 0xffffff
str r1, [r0]
ldr r0, = CAMDIVN
ldr r1, = 0
str r1, [r0]
ldr r0, = MPLLCON ; Configure MPLL
; Fin=16MHz, Fout=296.352MHz
ldr r1, = PLLVAL
str r1, [r0]
ldr r0, = UPLLCON ; Fin=16MHz, Fout=48MHz
ldr r1, = ((0x1a << 12) + (0x4 << 4) + 0x1) ; 16Mhz ;//c ksk 20051111
str r1, [r0]
mov r0, #0x2000
20
subs r0, r0, #1
bne %B20
;------------------------------------------------------------------------------
; Add for Power Management
ldr r1, =GSTATUS2 ; Determine Booting Mode
ldr r10, [r1]
;------------------------------------------------------------------------------
; Add for Power Management
tst r10, #0x2
beq BringUpWinCE ; Normal Mode Booting
;------------------------------------------------------------------------------
; Add for Power Management ?
BringUpWinCE
;------------------------------------------------------------------------------
; Initialize memory controller
add r0, pc, #MEMCTRLTAB - (. + 8)
ldr r1, = BWSCON ; BWSCON Address
add r2, r0, #52 ; End address of MEMCTRLTAB
40 ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne %B40
; b led_loop ;//+ ksk 20060207
ldr r0, = GPFDAT
mov r1, #0x60
str r1, [r0]
;------------------------------------------------------------------------------
; Copy boot loader to memory
ands r9, pc, #0xFF000000 ; see if we are in flash or in ram
bne %f20 ; go ahead if we are already in ram
; This is the loop that perform copying.
ldr r0, = 0x38000 ; offset into the RAM
add r0, r0, #PHYBASE ; add physical base
mov r1, r0 ; (r1) copy destination
ldr r2, =0x0 ; (r2) flash started at physical address 0
ldr r3, =0x10000 ; counter (0x40000/4)
10 ldr r4, [r2], #4
str r4, [r1], #4
subs r3, r3, #1
bne %b10
; Restart from the RAM position after copying.
mov pc, r0
nop
nop
nop
; Shouldn't get here.
b .
INCLUDE oemaddrtab_cfg.inc
; Compute physical address of the OEMAddressTable.
20 add r11, pc, #g_oalAddressTable - (. + 8)
ldr r10, =PTs ; (r10) = 1st level page table
; Setup 1st level page table (using section descriptor)
; Fill in first level page table entries to create "un-mapped" regions
; from the contents of the MemoryMap array.
;
; (r10) = 1st level page table
; (r11) = ptr to MemoryMap array
add r10, r10, #0x2000 ; (r10) = ptr to 1st PTE for "unmapped space"
mov r0, #0x0E ; (r0) = PTE for 0: 1MB cachable bufferable
orr r0, r0, #0x400 ; set kernel r/w permission
25 mov r1, r11 ; (r1) = ptr to MemoryMap array
30 ldr r2, [r1], #4 ; (r2) = virtual address to map Bank at
ldr r3, [r1], #4 ; (r3) = physical address to map from
ldr r4, [r1], #4 ; (r4) = num MB to map
cmp r4, #0 ; End of table?
beq %f40
ldr r5, =0x1FF00000
and r2, r2, r5 ; VA needs 512MB, 1MB aligned.
ldr r5, =0xFFF00000
and r3, r3, r5 ; PA needs 4GB, 1MB aligned.
add r2, r10, r2, LSR #18
add r0, r0, r3 ; (r0) = PTE for next physical page
35 str r0, [r2], #4
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