?? prev_cmp_schk.qmsg
字號:
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Web Edition " "Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 27 21:14:19 2007 " "Info: Processing started: Tue Nov 27 21:14:19 2007" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off SCHK -c SCHK " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off SCHK -c SCHK" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" { } { { "SCHK.vhd" "" { Text "D:/EDA/XLJC/SCHK.vhd" 4 -1 0 } } { "d:/quartus7.1/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus7.1/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register Q\[2\] Q\[0\] 250.0 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 250.0 MHz between source register \"Q\[2\]\" and destination register \"Q\[0\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.0 ns 2.0 ns 4.0 ns " "Info: fmax restricted to Clock High delay (2.0 ns) plus Clock Low delay (2.0 ns) : restricted to 4.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.100 ns + Longest register register " "Info: + Longest register to register delay is 1.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q\[2\] 1 REG LC2_E49 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_E49; Fanout = 4; REG Node = 'Q\[2\]'" { } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q[2] } "NODE_NAME" } } { "SCHK.vhd" "" { Text "D:/EDA/XLJC/SCHK.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.000 ns) 1.100 ns Q\[0\] 2 REG LC1_E49 4 " "Info: 2: + IC(0.100 ns) + CELL(1.000 ns) = 1.100 ns; Loc. = LC1_E49; Fanout = 4; REG Node = 'Q\[0\]'" { } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.100 ns" { Q[2] Q[0] } "NODE_NAME" } } { "SCHK.vhd" "" { Text "D:/EDA/XLJC/SCHK.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.000 ns ( 90.91 % ) " "Info: Total cell delay = 1.000 ns ( 90.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.100 ns ( 9.09 % ) " "Info: Total interconnect delay = 0.100 ns ( 9.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.100 ns" { Q[2] Q[0] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.100 ns" { Q[2] Q[0] } { 0.000ns 0.100ns } { 0.000ns 1.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.600 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_53 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_53; Fanout = 3; CLK Node = 'CLK'" { } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SCHK.vhd" "" { Text "D:/EDA/XLJC/SCHK.vhd" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.600 ns) + CELL(0.000 ns) 5.600 ns Q\[0\] 2 REG LC1_E49 4 " "Info: 2: + IC(3.600 ns) + CELL(0.000 ns) = 5.600 ns; Loc. = LC1_E49; Fanout = 4; REG Node = 'Q\[0\]'" { } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { CLK Q[0] } "NODE_NAME" } } { "SCHK.vhd" "" { Text "D:/EDA/XLJC/SCHK.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 35.71 % ) " "Info: Total cell delay = 2.000 ns ( 35.71 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.600 ns ( 64.29 % ) " "Info: Total interconnect delay = 3.600 ns ( 64.29 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "5.600 ns" { CLK Q[0] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "5.600 ns" { CLK CLK~out Q[0] } { 0.000ns 0.000ns 3.600ns } { 0.000ns 2.000ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 5.600 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_53 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_53; Fanout = 3; CLK Node = 'CLK'" { } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SCHK.vhd" "" { Text "D:/EDA/XLJC/SCHK.vhd" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.600 ns) + CELL(0.000 ns) 5.600 ns Q\[2\] 2 REG LC2_E49 4 " "Info: 2: + IC(3.600 ns) + CELL(0.000 ns) = 5.600 ns; Loc. = LC2_E49; Fanout = 4; REG Node = 'Q\[2\]'" { } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { CLK Q[2] } "NODE_NAME" } } { "SCHK.vhd" "" { Text "D:/EDA/XLJC/SCHK.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 35.71 % ) " "Info: Total cell delay = 2.000 ns ( 35.71 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.600 ns ( 64.29 % ) " "Info: Total interconnect delay = 3.600 ns ( 64.29 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "5.600 ns" { CLK Q[2] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "5.600 ns" { CLK CLK~out Q[2] } { 0.000ns 0.000ns 3.600ns } { 0.000ns 2.000ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "5.600 ns" { CLK Q[0] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "5.600 ns" { CLK CLK~out Q[0] } { 0.000ns 0.000ns 3.600ns } { 0.000ns 2.000ns 0.000ns } "" } } { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "5.600 ns" { CLK Q[2] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "5.600 ns" { CLK CLK~out Q[2] } { 0.000ns 0.000ns 3.600ns } { 0.000ns 2.000ns 0.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.800 ns + " "Info: + Micro clock to output delay of source is 0.800 ns" { } { { "SCHK.vhd" "" { Text "D:/EDA/XLJC/SCHK.vhd" 14 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" { } { { "SCHK.vhd" "" { Text "D:/EDA/XLJC/SCHK.vhd" 14 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.100 ns" { Q[2] Q[0] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "1.100 ns" { Q[2] Q[0] } { 0.000ns 0.100ns } { 0.000ns 1.000ns } "" } } { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "5.600 ns" { CLK Q[0] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "5.600 ns" { CLK CLK~out Q[0] } { 0.000ns 0.000ns 3.600ns } { 0.000ns 2.000ns 0.000ns } "" } } { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "5.600 ns" { CLK Q[2] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "5.600 ns" { CLK CLK~out Q[2] } { 0.000ns 0.000ns 3.600ns } { 0.000ns 2.000ns 0.000ns } "" } } } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0} } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q[0] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { Q[0] } { } { } "" } } { "SCHK.vhd" "" { Text "D:/EDA/XLJC/SCHK.vhd" 14 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "Q\[2\] DIN CLK 1.500 ns register " "Info: tsu for register \"Q\[2\]\" (data pin = \"DIN\", clock pin = \"CLK\") is 1.500 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns + Longest pin register " "Info: + Longest pin to register delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns DIN 1 PIN PIN_55 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 3; PIN Node = 'DIN'" { } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { DIN } "NODE_NAME" } } { "SCHK.vhd" "" { Text "D:/EDA/XLJC/SCHK.vhd" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(1.000 ns) 6.500 ns Q\[2\] 2 REG LC2_E49 4 " "Info: 2: + IC(3.500 ns) + CELL(1.000 ns) = 6.500 ns; Loc. = LC2_E49; Fanout = 4; REG Node = 'Q\[2\]'" { } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { DIN Q[2] } "NODE_NAME" } } { "SCHK.vhd" "" { Text "D:/EDA/XLJC/SCHK.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 46.15 % ) " "Info: Total cell delay = 3.000 ns ( 46.15 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.500 ns ( 53.85 % ) " "Info: Total interconnect delay = 3.500 ns ( 53.85 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { DIN Q[2] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { DIN DIN~out Q[2] } { 0.000ns 0.000ns 3.500ns } { 0.000ns 2.000ns 1.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" { } { { "SCHK.vhd" "" { Text "D:/EDA/XLJC/SCHK.vhd" 14 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.600 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_53 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_53; Fanout = 3; CLK Node = 'CLK'" { } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SCHK.vhd" "" { Text "D:/EDA/XLJC/SCHK.vhd" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.600 ns) + CELL(0.000 ns) 5.600 ns Q\[2\] 2 REG LC2_E49 4 " "Info: 2: + IC(3.600 ns) + CELL(0.000 ns) = 5.600 ns; Loc. = LC2_E49; Fanout = 4; REG Node = 'Q\[2\]'" { } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { CLK Q[2] } "NODE_NAME" } } { "SCHK.vhd" "" { Text "D:/EDA/XLJC/SCHK.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 35.71 % ) " "Info: Total cell delay = 2.000 ns ( 35.71 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.600 ns ( 64.29 % ) " "Info: Total interconnect delay = 3.600 ns ( 64.29 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "5.600 ns" { CLK Q[2] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "5.600 ns" { CLK CLK~out Q[2] } { 0.000ns 0.000ns 3.600ns } { 0.000ns 2.000ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "6.500 ns" { DIN Q[2] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "6.500 ns" { DIN DIN~out Q[2] } { 0.000ns 0.000ns 3.500ns } { 0.000ns 2.000ns 1.000ns } "" } } { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "5.600 ns" { CLK Q[2] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "5.600 ns" { CLK CLK~out Q[2] } { 0.000ns 0.000ns 3.600ns } { 0.000ns 2.000ns 0.000ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK AB Q\[0\] 15.100 ns register " "Info: tco from clock \"CLK\" to destination pin \"AB\" through register \"Q\[0\]\" is 15.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 5.600 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_53 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_53; Fanout = 3; CLK Node = 'CLK'" { } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SCHK.vhd" "" { Text "D:/EDA/XLJC/SCHK.vhd" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.600 ns) + CELL(0.000 ns) 5.600 ns Q\[0\] 2 REG LC1_E49 4 " "Info: 2: + IC(3.600 ns) + CELL(0.000 ns) = 5.600 ns; Loc. = LC1_E49; Fanout = 4; REG Node = 'Q\[0\]'" { } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { CLK Q[0] } "NODE_NAME" } } { "SCHK.vhd" "" { Text "D:/EDA/XLJC/SCHK.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 35.71 % ) " "Info: Total cell delay = 2.000 ns ( 35.71 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.600 ns ( 64.29 % ) " "Info: Total interconnect delay = 3.600 ns ( 64.29 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "5.600 ns" { CLK Q[0] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "5.600 ns" { CLK CLK~out Q[0] } { 0.000ns 0.000ns 3.600ns } { 0.000ns 2.000ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.800 ns + " "Info: + Micro clock to output delay of source is 0.800 ns" { } { { "SCHK.vhd" "" { Text "D:/EDA/XLJC/SCHK.vhd" 14 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.700 ns + Longest register pin " "Info: + Longest register to pin delay is 8.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q\[0\] 1 REG LC1_E49 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_E49; Fanout = 4; REG Node = 'Q\[0\]'" { } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q[0] } "NODE_NAME" } } { "SCHK.vhd" "" { Text "D:/EDA/XLJC/SCHK.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.400 ns) 1.500 ns Equal0~12 2 COMB LC4_E49 1 " "Info: 2: + IC(0.100 ns) + CELL(1.400 ns) = 1.500 ns; Loc. = LC4_E49; Fanout = 1; COMB Node = 'Equal0~12'" { } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { Q[0] Equal0~12 } "NODE_NAME" } } { "SCHK.vhd" "" { Text "D:/EDA/XLJC/SCHK.vhd" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.200 ns) 8.700 ns AB 3 PIN PIN_206 0 " "Info: 3: + IC(1.000 ns) + CELL(6.200 ns) = 8.700 ns; Loc. = PIN_206; Fanout = 0; PIN Node = 'AB'" { } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "7.200 ns" { Equal0~12 AB } "NODE_NAME" } } { "SCHK.vhd" "" { Text "D:/EDA/XLJC/SCHK.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.600 ns ( 87.36 % ) " "Info: Total cell delay = 7.600 ns ( 87.36 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns ( 12.64 % ) " "Info: Total interconnect delay = 1.100 ns ( 12.64 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "8.700 ns" { Q[0] Equal0~12 AB } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "8.700 ns" { Q[0] Equal0~12 AB } { 0.000ns 0.100ns 1.000ns } { 0.000ns 1.400ns 6.200ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "5.600 ns" { CLK Q[0] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "5.600 ns" { CLK CLK~out Q[0] } { 0.000ns 0.000ns 3.600ns } { 0.000ns 2.000ns 0.000ns } "" } } { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "8.700 ns" { Q[0] Equal0~12 AB } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "8.700 ns" { Q[0] Equal0~12 AB } { 0.000ns 0.100ns 1.000ns } { 0.000ns 1.400ns 6.200ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "Q\[0\] DIN CLK 0.000 ns register " "Info: th for register \"Q\[0\]\" (data pin = \"DIN\", clock pin = \"CLK\") is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.600 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_53 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_53; Fanout = 3; CLK Node = 'CLK'" { } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "SCHK.vhd" "" { Text "D:/EDA/XLJC/SCHK.vhd" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.600 ns) + CELL(0.000 ns) 5.600 ns Q\[0\] 2 REG LC1_E49 4 " "Info: 2: + IC(3.600 ns) + CELL(0.000 ns) = 5.600 ns; Loc. = LC1_E49; Fanout = 4; REG Node = 'Q\[0\]'" { } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { CLK Q[0] } "NODE_NAME" } } { "SCHK.vhd" "" { Text "D:/EDA/XLJC/SCHK.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 35.71 % ) " "Info: Total cell delay = 2.000 ns ( 35.71 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.600 ns ( 64.29 % ) " "Info: Total interconnect delay = 3.600 ns ( 64.29 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "5.600 ns" { CLK Q[0] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "5.600 ns" { CLK CLK~out Q[0] } { 0.000ns 0.000ns 3.600ns } { 0.000ns 2.000ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.700 ns + " "Info: + Micro hold delay of destination is 0.700 ns" { } { { "SCHK.vhd" "" { Text "D:/EDA/XLJC/SCHK.vhd" 14 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.300 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns DIN 1 PIN PIN_55 3 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 3; PIN Node = 'DIN'" { } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { DIN } "NODE_NAME" } } { "SCHK.vhd" "" { Text "D:/EDA/XLJC/SCHK.vhd" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(0.800 ns) 6.300 ns Q\[0\] 2 REG LC1_E49 4 " "Info: 2: + IC(3.500 ns) + CELL(0.800 ns) = 6.300 ns; Loc. = LC1_E49; Fanout = 4; REG Node = 'Q\[0\]'" { } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "4.300 ns" { DIN Q[0] } "NODE_NAME" } } { "SCHK.vhd" "" { Text "D:/EDA/XLJC/SCHK.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 44.44 % ) " "Info: Total cell delay = 2.800 ns ( 44.44 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.500 ns ( 55.56 % ) " "Info: Total interconnect delay = 3.500 ns ( 55.56 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "6.300 ns" { DIN Q[0] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "6.300 ns" { DIN DIN~out Q[0] } { 0.000ns 0.000ns 3.500ns } { 0.000ns 2.000ns 0.800ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "5.600 ns" { CLK Q[0] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "5.600 ns" { CLK CLK~out Q[0] } { 0.000ns 0.000ns 3.600ns } { 0.000ns 2.000ns 0.000ns } "" } } { "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus7.1/quartus/bin/TimingClosureFloorplan.fld" "" "6.300 ns" { DIN Q[0] } "NODE_NAME" } } { "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus7.1/quartus/bin/Technology_Viewer.qrui" "6.300 ns" { DIN DIN~out Q[0] } { 0.000ns 0.000ns 3.500ns } { 0.000ns 2.000ns 0.800ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "114 " "Info: Allocated 114 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 27 21:14:21 2007 " "Info: Processing ended: Tue Nov 27 21:14:21 2007" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 3 s " "Info: Quartus II Full Compilation was successful. 0 errors, 3 warnings" { } { } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
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