?? lcd_control.v
字號:
4'b0100 : sf_d_temp = 8'b00110100; //4 4'b0101 : sf_d_temp = 8'b00110101; //5 4'b0110 : sf_d_temp = 8'b00110110; //6 4'b0111 : sf_d_temp = 8'b00110111; //7 4'b1000 : sf_d_temp = 8'b00111000; //8 4'b1001 : sf_d_temp = 8'b00111001; //9 default : sf_d_temp = 8'b00101101; //[-] endcase if (count == `TIME3) begin next_state <= `lap_display3; control = 3'b101; state_flag <= 1'b1; end else if ((count > `TIME2) && (count <= `TIME3)) begin next_state <= `lap_display2; control = 3'b100; state_flag <= 1'b0; end else begin next_state <= `lap_display2; control = 3'b101; state_flag <= 1'b0; end end // case `lap_display3 : begin sf_d_temp = 8'b11000111; // Set Address hx47 if (count == `TIME3) begin next_state <= `lap_display4; control = 3'b001; state_flag <= 1'b1; end else if ((count > `TIME2) && (count <= `TIME3)) begin next_state <= `lap_display3; control = 3'b000; state_flag <= 1'b0; end else begin next_state <= `lap_display3; control = 3'b001; state_flag <= 1'b0; end end // case `lap_display4 : begin sf_d_temp = 8'b00111010; // [colon] if (count == `TIME3) begin next_state <= `lap_display5; control = 3'b101; state_flag <= 1'b1; end else if ((count > `TIME2) && (count <= `TIME3)) begin next_state <= `lap_display4; control = 3'b100; state_flag <= 1'b0; end else begin next_state <= `lap_display4; control = 3'b101; state_flag <= 1'b0; end end // case `lap_display5 : begin sf_d_temp = 8'b11001000; // Set Address hx48 if (count == `TIME3) begin next_state <= `lap_display6; control = 3'b001; state_flag <= 1'b1; end else if ((count > `TIME2) && (count <= `TIME3)) begin next_state <= `lap_display5; control = 3'b000; state_flag <= 1'b0; end else begin next_state <= `lap_display5; control = 3'b001; state_flag <= 1'b0; end end // case `lap_display6 : begin // Display tens of seconds digit case (lap_tens) 4'b0000 : sf_d_temp = 8'b00110000; //0 4'b0001 : sf_d_temp = 8'b00110001; //1 4'b0010 : sf_d_temp = 8'b00110010; //2 4'b0011 : sf_d_temp = 8'b00110011; //3 4'b0100 : sf_d_temp = 8'b00110100; //4 4'b0101 : sf_d_temp = 8'b00110101; //5 4'b0110 : sf_d_temp = 8'b00110110; //6 4'b0111 : sf_d_temp = 8'b00110111; //7 4'b1000 : sf_d_temp = 8'b00111000; //8 4'b1001 : sf_d_temp = 8'b00111001; //9 default : sf_d_temp = 8'b00101101; //[-] endcase if (count == `TIME3) begin next_state <= `lap_display7; control = 3'b101; state_flag <= 1'b1; end else if ((count > `TIME2) && (count <= `TIME3)) begin next_state <= `lap_display6; control = 3'b100; state_flag <= 1'b0; end else begin next_state <= `lap_display6; control = 3'b101; state_flag <= 1'b0; end end // case `lap_display7 : begin sf_d_temp = 8'b11001001; // Set Address hx49 if (count == `TIME3) begin next_state <= `lap_display8; control = 3'b001; state_flag <= 1'b1; end else if ((count > `TIME2) && (count <= `TIME3)) begin next_state <= `lap_display7; control = 3'b000; state_flag <= 1'b0; end else begin next_state <= `lap_display7; control = 3'b001; state_flag <= 1'b0; end end // case `lap_display8 : begin // Display seconds digit case (lap_ones) 4'b0000 : sf_d_temp = 8'b00110000; //0 4'b0001 : sf_d_temp = 8'b00110001; //1 4'b0010 : sf_d_temp = 8'b00110010; //2 4'b0011 : sf_d_temp = 8'b00110011; //3 4'b0100 : sf_d_temp = 8'b00110100; //4 4'b0101 : sf_d_temp = 8'b00110101; //5 4'b0110 : sf_d_temp = 8'b00110110; //6 4'b0111 : sf_d_temp = 8'b00110111; //7 4'b1000 : sf_d_temp = 8'b00111000; //8 4'b1001 : sf_d_temp = 8'b00111001; //9 default : sf_d_temp = 8'b00101101; //[-] endcase if (count == `TIME3) begin next_state <= `lap_display9; control = 3'b101; state_flag <= 1'b1; end else if ((count > `TIME2) && (count <= `TIME3)) begin next_state <= `lap_display8; control = 3'b100; state_flag <= 1'b0; end else begin next_state <= `lap_display8; control = 3'b101; state_flag <= 1'b0; end end // case `lap_display9 : begin sf_d_temp = 8'b11001010; // Set Address hx4A if (count == `TIME3) begin next_state <= `lap_display10; control = 3'b001; state_flag <= 1'b1; end else if ((count > `TIME2) && (count <= `TIME3)) begin next_state <= `lap_display9; control = 3'b000; state_flag <= 1'b0; end else begin next_state <= `lap_display9; control = 3'b001; state_flag <= 1'b0; end end // case `lap_display10 : begin sf_d_temp = 8'b00111010; // [colon] if (count == `TIME3) begin next_state <= `lap_display11; control = 3'b101; state_flag <= 1'b1; end else if ((count > `TIME2) && (count <= `TIME3)) begin next_state <= `lap_display10; control = 3'b100; state_flag <= 1'b0; end else begin next_state <= `lap_display10; control = 3'b101; state_flag <= 1'b0; end end // case `lap_display11 : begin sf_d_temp = 8'b11001011; // Set Address hx4B if (count == `TIME3) begin next_state <= `lap_display12; control = 3'b001; state_flag <= 1'b1; end else if ((count > `TIME2) && (count <= `TIME3)) begin next_state <= `lap_display11; control = 3'b000; state_flag <= 1'b0; end else begin next_state <= `lap_display11; control = 3'b001; state_flag <= 1'b0; end end // case `lap_display12 : begin // Display tenths of second digit case (lap_tenths) 4'b0000 : sf_d_temp = 8'b00110000; //0 4'b0001 : sf_d_temp = 8'b00110001; //1 4'b0010 : sf_d_temp = 8'b00110010; //2 4'b0011 : sf_d_temp = 8'b00110011; //3 4'b0100 : sf_d_temp = 8'b00110100; //4 4'b0101 : sf_d_temp = 8'b00110101; //5 4'b0110 : sf_d_temp = 8'b00110110; //6 4'b0111 : sf_d_temp = 8'b00110111; //7 4'b1000 : sf_d_temp = 8'b00111000; //8 4'b1001 : sf_d_temp = 8'b00111001; //9 default : sf_d_temp = 8'b00101101; //[-] endcase if (count == `TIME3) begin next_state <= `lap_display13; control = 3'b101; state_flag <= 1'b1; end else if ((count > `TIME2) && (count <= `TIME3)) begin next_state <= `lap_display12; control = 3'b100; state_flag <= 1'b0; end else begin next_state <= `lap_display12; control = 3'b101; state_flag <= 1'b0; end end // case `lap_display13 : begin sf_d_temp = 8'b11001100; // Set Address hx4C if (count == `TIME3) begin next_state <= `lap_display14; control = 3'b001; state_flag <= 1'b1; end else if ((count > `TIME2) && (count <= `TIME3)) begin next_state <= `lap_display13; control = 3'b000; state_flag <= 1'b0; end else begin next_state <= `lap_display13; control = 3'b001; state_flag <= 1'b0; end end // lap_display13 `lap_display14 : begin // Display hundredths of second digit case (lap_hundredths) 4'b0000 : sf_d_temp = 8'b00110000; //0 4'b0001 : sf_d_temp = 8'b00110001; //1 4'b0010 : sf_d_temp = 8'b00110010; //2 4'b0011 : sf_d_temp = 8'b00110011; //3 4'b0100 : sf_d_temp = 8'b00110100; //4 4'b0101 : sf_d_temp = 8'b00110101; //5 4'b0110 : sf_d_temp = 8'b00110110; //6 4'b0111 : sf_d_temp = 8'b00110111; //7 4'b1000 : sf_d_temp = 8'b00111000; //8 4'b1001 : sf_d_temp = 8'b00111001; //9 default : sf_d_temp = 8'b00101101; //[-] endcase if (count == `TIME3) begin next_state <= `time_display1; control = 3'b101; state_flag <= 1'b1; set_lap_flag <= 1'b0; end else if ((count > `TIME2) && (count <= `TIME3)) begin next_state <= `lap_display14; control = 3'b100; state_flag <= 1'b0; end else begin next_state <= `lap_display14; control = 3'b101; state_flag <= 1'b0; end end // lap_display14 `donestate : begin control = 3'b100; sf_d_temp = 8'b00000000; if (count == `TIME3) begin next_state <= `donestate; state_flag <= 1'b1; end else begin next_state <= `donestate; state_flag <= 1'b0; end end // donestate endcaseend // always// set lap timealways @(posedge clk)begin if (rst & ~mode) begin lap_flag <= 1'b0; lap_min <= 4'b0000; lap_tens <= 4'b0000; lap_ones <= 4'b0000; lap_tenths <= 4'b0000; lap_hundredths <= 4'b0000; end else if (lap & mode) begin lap_flag <= 1'b1; lap_min <= minutes; lap_tens <= tens; lap_ones <= ones; lap_tenths <= tenths; lap_hundredths <= hundredths; end else begin lap_min <= lap_min; lap_tens <=lap_tens; lap_ones <= lap_ones; lap_tenths <= lap_tenths; lap_hundredths <= lap_hundredths; lap_flag <= set_lap_flag; endend // always // sets timer or clock modealways @(posedge clk)begin if (rst) begin timer_flag <= 1'b0; next_mode_state <= 1'b0; clock_flag <= 1'b0; end else if (mode_state) begin if (mode) begin next_mode_state <= 1'b1; clock_flag <= set_clock_flag; end else begin next_mode_state <= 1'b0; timer_flag <= 1'b1; end end // if else if (~mode_state) begin if (~mode) begin next_mode_state <= 1'b0; timer_flag <= set_timer_flag; end else begin next_mode_state <= 1'b1; clock_flag <= 1'b1; end end // if end // always //registers state variablesalways @ (posedge clk)begin sf_d <= sf_d_temp; count <= count_temp; if (rst) begin state <= `waiting; mode_state <= 1'b0; count_temp <= 0; end else if (state_flag) begin state <= next_state; mode_state <= next_mode_state; count_temp <= 0; end else begin state <= next_state; mode_state <= next_mode_state; count_temp <= count_temp + 1; endend // always endmodule //lcd_control
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