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// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file timer_preset.v when simulating
// the core, timer_preset. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".

`timescale 1ns/1ps

module timer_preset(
	a,
	spo);


input [5 : 0] a;
output [19 : 0] spo;

// synthesis translate_off

      DIST_MEM_GEN_V3_2 #(
		.C_ADDR_WIDTH(6),
		.C_DEFAULT_DATA("0"),
		.C_DEPTH(64),
		.C_HAS_CLK(0),
		.C_HAS_D(0),
		.C_HAS_DPO(0),
		.C_HAS_DPRA(0),
		.C_HAS_I_CE(0),
		.C_HAS_QDPO(0),
		.C_HAS_QDPO_CE(0),
		.C_HAS_QDPO_CLK(0),
		.C_HAS_QDPO_RST(0),
		.C_HAS_QDPO_SRST(0),
		.C_HAS_QSPO(0),
		.C_HAS_QSPO_CE(0),
		.C_HAS_QSPO_RST(0),
		.C_HAS_QSPO_SRST(0),
		.C_HAS_SPO(1),
		.C_HAS_SPRA(0),
		.C_HAS_WE(0),
		.C_MEM_INIT_FILE("timer_preset.mif"),
		.C_MEM_TYPE(0),
		.C_PIPELINE_STAGES(0),
		.C_QCE_JOINED(0),
		.C_QUALIFY_WE(0),
		.C_READ_MIF(1),
		.C_REG_A_D_INPUTS(0),
		.C_REG_DPRA_INPUT(0),
		.C_SYNC_ENABLE(1),
		.C_WIDTH(20))
	inst (
		.A(a),
		.SPO(spo),
		.D(),
		.DPRA(),
		.SPRA(),
		.CLK(),
		.WE(),
		.I_CE(),
		.QSPO_CE(),
		.QDPO_CE(),
		.QDPO_CLK(),
		.QSPO_RST(),
		.QDPO_RST(),
		.QSPO_SRST(),
		.QDPO_SRST(),
		.DPO(),
		.QSPO(),
		.QDPO());


// synthesis translate_on

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of timer_preset is "black_box"

endmodule