################################################################ Xilinx Core Generator version IP1_J.12# Date: Thu Mar 15 16:38:03 2007#################################################################  This file contains the customisation parameters for a#  Xilinx CORE Generator IP GUI. It is strongly recommended#  that you do not manually alter this file as it may cause#  unexpected and unsupported behavior.################################################################# BEGIN Project OptionsSET addpads = FalseSET asysymbol = TrueSET busformat = BusFormatAngleBracketNotRippedSET createndf = FalseSET designentry = VHDLSET device = xc3s700aSET devicefamily = spartan3aSET flowvendor = Foundation_iSESET formalverification = FalseSET foundationsym = FalseSET implementationfiletype = NgcSET package = fg484SET removerpms = FalseSET simulationfiles = BehavioralSET speedgrade = -4SET verilogsim = TrueSET vhdlsim = True# END Project Options# BEGIN SelectSELECT Distributed_Memory_Generator family Xilinx,_Inc. 3.2# END Select# BEGIN ParametersCSET ce_overrides=ce_overrides_sync_controlsCSET coefficient_file=C:/Temp/tutorial/wtut_sc/wtut_sc_completed/definition1_times.coeCSET common_output_ce=falseCSET common_output_clk=falseCSET component_name=timer_presetCSET data_width=20CSET default_data=0CSET default_data_radix=16CSET depth=64CSET dual_port_address=non_registeredCSET dual_port_output_clock_enable=falseCSET input_clock_enable=falseCSET input_options=non_registeredCSET memory_type=romCSET output_options=non_registeredCSET pipeline_stages=0CSET qualify_we_with_i_ce=falseCSET reset_qdpo=falseCSET reset_qspo=falseCSET single_port_output_clock_enable=falseCSET sync_reset_qdpo=falseCSET sync_reset_qspo=false# END ParametersGENERATE# CRC: 5b713561