package n_bit_int is    subtype word26 is integer range 0 to 2**26-1;end n_bit_int;library work;use work.n_bit_int.all;library ieee;    use ieee.std_logic_1164.all;    use ieee.std_logic_arith.all;    use ieee.std_logic_unsigned.all;    entity cic4 is    port (          clk : in std_logic;          x_in :in std_logic_vector (7 downto 0);          y_out : out std_logic_vector (8 downto 0)); end cic4;architecture cicImpl of cic4 is    type state_type is (hold, sample);    signal state : state_type;    signal count : integer range 0 to 40;    signal clk2  : std_logic;    signal x     : std_logic_vector (7 downto 0);    signal sxtx  : std_logic_vector (25 downto 0);    signal i0,i1,i2,i3: word26;    signal i2d1,i2d2,i2d3,i2d4,c1,c0 : word26;    signal c1d1,c1d2,c1d3,c1d4,c2: word26;    signal c2d1,c2d2,c2d3,c2d4,c3: word26;    signal c3d1,c3d2,c3d3,c3d4,c4: word26;    begin        fsm: process    begin         wait until clk='0';         case state is           when hold=>              if count <31 then                   state <= hold;              else                   state <=sample;              end if;          when others =>              state <=hold;         end case;    end process fsm;        sxt:  process (x)    begin         sxtx (7 downto 0) <=x;         for k in 25 downto 8 loop          sxtx (k) <= x(x'high);        end loop;   end process sxt;      int: process    begin         wait until clk='1';          x <= x_in;          i0 <= i0+ conv_integer (sxtx);          i1 <= i1+i0;          i2 <= i2+i1;
			 i3 <= i3+i2;        case state is            when sample =>                c0 <= i3;                count <= 0;            when others =>                count <= count + 1;        end case;      if (count > 16) and (count <32) then         clk2 <= '1';      else         clk2 <= '0';      end if;end process int;comb :processbegin   wait until clk2='1';     i2d1 <= c0;     i2d2 <= i2d1;     c1   <= c0 - i2d2;     c1d1 <= c1;     c1d2 <= c1d1;     c2   <= c1- c1d2;     c2d1 <= c2;     c2d2 <= c2d1;     c3   <= c2-c2d2;
	 
	  c3d1 <= c3;     c3d2 <= c3d1;     c4   <= c3-c3d2;	  
	  end process comb;y_out <= conv_std_logic_vector (c3/2**17, 9);end cicImpl;