Entity testbench is  End testbench;    architecture test of testbench is        component nandgate          port ( in1: in bit_vector ( 3 downto 0);                 in2: in bit_vector ( 3 downto 0);                 q:   out bit_vector ( 3 downto 0));        End component;         Signal a,b,q1: bit_vector ( 3 downto 0);        Signal c: bit_vector (7 downto 0);        begin             C1: nandgate port map (a,b,q1);             a<= c ( 7 downto 4);            b<= c ( 3 downto 0);            c<= "00000000",                "10010011" after 10 ns,                "10010101" after 20 ns,                "01011010" after 30 ns,                "10010110" after 40 ns,                "01011101" after 50 ns,                "10010100" after 60 ns;        End test;