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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN"><html><head><link rel="STYLESHEET" type="text/css" href="wrs.css"><title> Shared-Memory Objects </title></head><body bgcolor="FFFFFF"><p class="navbar" align="right"><a href="index.html"><img border="0" alt="[Contents]" src="icons/contents.gif"></a><a href="GuideIX.html"><img border="0" alt="[Index]" src="icons/index.gif"></a><a href="c-smo.html"><img border="0" alt="[Top]" src="icons/top.gif"></a><a href="c-smo2.html"><img border="0" alt="[Prev]" src="icons/prev.gif"></a><a href="c-smo4.html"><img border="0" alt="[Next]" src="icons/next.gif"></a></p><font face="Helvetica, sans-serif" class="sans"><h3 class="H2"><i><a name="85285">6.3 Internal Considerations</a></i></h3></font><font face="Helvetica, sans-serif" class="sans"><h4 class="H3"><i><a name="85286">6.3.1 System Requirements</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="85288"> </a>The shared-memory region used by shared-memory objects must be visible to all CPUs in the system. Either dual-ported memory on the master CPU (CPU 0) or a separate memory board can be used. The shared-memory objects' anchor must be in the same address space as the shared-memory region. Note that the memory does <i class="emphasis">not</i><b> </b>have to appear at the same address for all CPUs.</p></dl></dl><dl class="margin"><dd><p class="table" callout><table border="0" cellpadding="0" cellspacing="0"><tr valign="top"><td valign="top" width="40"><br><img border="0" alt="*" src="icons/caution.gif"></td><td><hr><div class="CalloutCell"><a name="86504"><b class="symbol_UC"><font face="Helvetica, sans-serif" size="-1" class="sans">CAUTION: </font></b></a>Boards that make use of VxMP must support hardware test-and-set (indivisible read-modify-write cycle). PowerPC is an exception; see <a href="x-ppc.html#84368"><i class="title">F. PowerPC</i></a>.</div></td></tr><tr valign="top"><td></td><td><hr></td></tr><tr valign="middle"><td colspan="20"></td></tr></table></p callout><dl class="margin"><dd><p class="Body"><a name="85301"> </a>All CPUs in the system must support indivisible read-modify-write cycle across the (VME) bus. The indivisible RMW is used by the spin-lock mechanism to gain exclusive access to internal shared data structures; see <a href="c-smo3.html#88047"><i class="title">6.3.2 Spin-lock Mechanism</i></a> for details. Because all the boards must support a hardware test-and-set, the constant <b class="symbol_UC">SM_TAS_TYPE </b>must be set to <b class="symbol_UC">SM_TAS_HARD</b> on the <b class="guiLabel"><font face="Helvetica, sans-serif" size="-1" class="sans">Parameters</font></b> tab of the project facility VxWorks view.</p><dd><p class="Body"><a name="85306"> </a>CPUs must be notified of any event that affects them. The preferred method is for the CPU initiating the event to interrupt the affected CPU. The use of interrupts is dependent on the capabilities of the hardware. If interrupts cannot be used, a polling scheme can be employed, although this generally results in a significant performance penalty.</p><dd><p class="Body"><a name="88045"> </a>The maximum number of CPUs that can use shared-memory objects is 20 (CPUs numbered 0 through 19). The practical maximum is usually a smaller number that depends on the CPU, bus bandwidth, and application.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H3"><i><a name="88047">6.3.2 Spin-lock Mechanism</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="88048"> </a>Internal shared-memory object data structures are protected against concurrent access by a <i class="term">spin-lock mechanism</i>. The spin-lock mechanism is a loop where an attempt is made to gain exclusive access to a resource (in this case an internal data structure). An indivisible hardware read-modify-write cycle (hardware test-and-set) is used for this mutual exclusion. If the first attempt to take the lock fails, multiple attempts are made, each with a decreasing random delay between one attempt and the next. The average time it takes between the original attempt to take the lock and the first retry is 70 microseconds on an MC68030 at 20MHz. Operating time for the spin-lock cycle varies greatly because it is affected by the processor cache, access time to shared memory, and bus traffic. If the lock is not obtained after the maximum number of tries specified by <b class="symbol_UC">SM_OBJ_MAX_TRIES</b> (defined in the <b class="guiLabel"><font face="Helvetica, sans-serif" size="-1" class="sans">Params</font></b> tab of the properties window for shared memory objects in the VxWorks view), <b class="symbol_lc">errno</b> is set to <b class="symbol_UC">S_smObjLib_LOCK_TIMEOUT</b>. If this error occurs, set the maximum number of tries to a higher value. Note that any failure to take a spin-lock prevents proper functioning of shared-memory objects. In most cases, this is due to problems with the shared-memory configuration; see <a href="c-smo5.html#85682"><i class="title">6.5.2 Troubleshooting Techniques</i></a>.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H3"><i><a name="88062">6.3.3 Interrupt Latency</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="88064"> </a>For the duration of the spin-lock, interrupts are disabled to avoid the possibility of a task being preempted while holding the spin-lock. As a result, the interrupt latency of each processor in the system is increased. However, the interrupt latency added by shared-memory objects is constant for a particular CPU.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H3"><i><a name="85320">6.3.4 Restrictions</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="85321"> </a>Unlike local semaphores and message queues, shared-memory objects cannot be used at interrupt level. No routines that use shared-memory objects can be called from ISRs. An ISR is dedicated to handle time-critical processing associated with an external event; therefore, using shared-memory objects at interrupt time is not appropriate. On a multiprocessor system, run event-related time-critical processing on the CPU where the time-related interrupt occurred.</p><dd><p class="Body"><a name="88113"> </a>Note that shared-memory objects are allocated from dedicated shared-memory pools, and cannot be deleted. </p><dd><p class="Body"><a name="88115"> </a>When using shared-memory objects, the maximum number of each object type must be specified on the <b class="guiLabel"><font face="Helvetica, sans-serif" size="-1" class="sans">Params</font></b> tab of the properties window; see <a href="c-smo4.html#85430"><i class="title">6.4.3 Initializing the Shared-Memory Objects Package</i></a>. If applications are creating more than the specified maximum number of objects, it is possible to run out of memory. If this happens, the shared object creation routine returns an error and <b class="symbol_lc">errno</b> is set to <b class="symbol_UC">S_memLib_NOT_ENOUGH_MEM</b>. To solve this problem, first increase the maximum number of shared-memory objects of corresponding type; see <a href="c-smo4.html#87165">Table 6-5</a> for a list of the applicable configuration constants. This decreases the size of the shared-memory system pool because the shared-memory pool uses the remainder of the shared memory. If this is undesirable, increase both the number of the corresponding shared-memory objects and the size of the overall shared-memory region, <b class="symbol_UC">SM_OBJ_MEM_SIZE</b>. See <a href="c-smo4.html#85343"><i class="title">6.4 Configuration</i></a> for a discussion of the constants used for configuration.</p></dl></dl><font face="Helvetica, sans-serif" class="sans"><h4 class="H3"><i><a name="85335">6.3.5 Cache Coherency</a></i></h4></font><dl class="margin"><dl class="margin"><dd><p class="Body"><a name="87105"> </a>When dual-ported memory is used on some boards without MMU or bus snooping mechanisms, the data cache must be disabled for the shared-memory region on the master CPU. If you see the following error message, make sure that the constant <b class="symbol_UC">INCLUDE_CACHE_ENABLE</b> is not selected for inclusion in the VxWorks view:</p><dl class="margin"><dd><pre class="Code2"><b><a name="87109">usrSmObjInit - cache coherent buffer not available. Giving up.</a></b></pre></dl></dl></dl><a name="foot"><hr></a><p class="navbar" align="right"><a href="index.html"><img border="0" alt="[Contents]" src="icons/contents.gif"></a><a href="GuideIX.html"><img border="0" alt="[Index]" src="icons/index.gif"></a><a href="c-smo.html"><img border="0" alt="[Top]" src="icons/top.gif"></a><a href="c-smo2.html"><img border="0" alt="[Prev]" src="icons/prev.gif"></a><a href="c-smo4.html"><img border="0" alt="[Next]" src="icons/next.gif"></a></p></body></html><!---by WRS Documentation (), Wind River Systems, Inc. conversion tool: Quadralay WebWorks Publisher 4.0.11 template: CSS Template, Jan 1998 - Jefro --->?? 快捷鍵說明
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