#define  RXBPFTSTL   XREG( 0xDF38 )  /*  Reserved for test purposes                          */
#define  FSMSTATE    XREG( 0xDF39 )  /*  Finite State Machine Status                         */
#define  ADCTSTH     XREG( 0xDF3A )  /*  ADC Test High Byte                                  */
#define  ADCTSTL     XREG( 0xDF3B )  /*  ADC Test Low Byte                                   */
#define  DACTSTH     XREG( 0xDF3C )  /*  DAC Test High Byte                                  */
#define  DACTSTL     XREG( 0xDF3D )  /*  DAC Test Low Byte                                   */
#define  _XREGDF3E   XREG( 0xDF3E )  /*  reserved                                            */
#define  TOPTST      XREG( 0xDF3F )  /*  Reserved for test purposes                          */
#define  RESERVEDH   XREG( 0xDF40 )  /*  Reserved for test purposes                          */
#define  RESERVEDL   XREG( 0xDF41 )  /*  Reserved for test purposes                          */
#define  IEEE_ADDR0  XREG( 0xDF43 )  /*  IEEE Address Byte 0 (LSB)                           */
#define  IEEE_ADDR1  XREG( 0xDF44 )  /*  IEEE Address Byte 1                                 */
#define  IEEE_ADDR2  XREG( 0xDF45 )  /*  IEEE Address Byte 2                                 */
#define  IEEE_ADDR3  XREG( 0xDF46 )  /*  IEEE Address Byte 3                                 */
#define  IEEE_ADDR4  XREG( 0xDF47 )  /*  IEEE Address Byte 4                                 */
#define  IEEE_ADDR5  XREG( 0xDF48 )  /*  IEEE Address Byte 5                                 */
#define  IEEE_ADDR6  XREG( 0xDF49 )  /*  IEEE Address Byte 6                                 */
#define  IEEE_ADDR7  XREG( 0xDF4A )  /*  IEEE Address Byte 7 (MSB)                           */
#define  PANIDH      XREG( 0xDF4B )  /*  PAN Identifier High Byte                            */
#define  PANIDL      XREG( 0xDF4C )  /*  PAN Identifier Low Byte                             */
#define  SHORTADDRH  XREG( 0xDF4D )  /*  Short Address High Byte                             */
#define  SHORTADDRL  XREG( 0xDF4E )  /*  Short Address Low Byte                              */
#define  IOCFG0      XREG( 0xDF4F )  /*  I/O Configuration 0                                 */
#define  IOCFG1      XREG( 0xDF50 )  /*  I/O Configuration 1                                 */
#define  IOCFG2      XREG( 0xDF51 )  /*  I/O Configuration 2                                 */
#define  IOCFG3      XREG( 0xDF52 )  /*  I/O Configuration 3                                 */
#define  RXFIFOCNT   XREG( 0xDF53 )  /*  Rx FIFO Count                                       */
#define  FSMTC1      XREG( 0xDF54 )  /*  Finite State Machine Control                        */
#define  _XREGDF55   XREG( 0xDF55 )  /*  reserved                                            */
#define  _XREGDF56   XREG( 0xDF56 )  /*  reserved                                            */
#define  _XREGDF57   XREG( 0xDF57 )  /*  reserved                                            */
#define  _XREGDF58   XREG( 0xDF58 )  /*  reserved                                            */
#define  _XREGDF59   XREG( 0xDF59 )  /*  reserved                                            */
#define  _XREGDF5A   XREG( 0xDF5A )  /*  reserved                                            */
#define  _XREGDF5B   XREG( 0xDF5B )  /*  reserved                                            */
#define  _XREGDF5C   XREG( 0xDF5C )  /*  reserved                                            */
#define  _XREGDF5D   XREG( 0xDF5D )  /*  reserved                                            */
#define  _XREGDF5E   XREG( 0xDF5E )  /*  reserved                                            */
#define  _XREGDF5F   XREG( 0xDF5F )  /*  reserved                                            */
#define  CHVER       XREG( 0xDF60 )  /*  Chip Version                                        */
#define  CHIPID      XREG( 0xDF61 )  /*  Chip Identification                                 */
#define  RFSTATUS    XREG( 0xDF62 )  /*  RF Status                                           */
#define  XOSC32M     XREG( 0xDF63 )  /*  32 MHz Crystal Oscillator Control                   */
#define  IRQSRC      XREG( 0xDF64 )  /*  RF Interrupt Source                                 */


/* ------------------------------------------------------------------------------------------------
 *                                      Xdata Mapped SFRs
 * ------------------------------------------------------------------------------------------------
 */

/*
 *   Most SFRs are also accessible through XDATA address space.  The register definitions for
 *   this type of access are listed below.  The register names are identical to the SFR names
 *   but with the prefix X_ to denote an XDATA register.
 *
 *   Some SFRs are not accessible through XDATA space.  For clarity, entries are included for these
 *   registers.  They have a prefix of _NA to denote "not available."
 *
 *   For register descriptions, refer to the actual SFR declartions elsewhere in this file.
 */
#define  _NA_P0      XREG( 0xDF80 )
#define  _NA_SP      XREG( 0xDF81 )
#define  _NA_DPL0    XREG( 0xDF82 )
#define  _NA_DPH0    XREG( 0xDF83 )
#define  _NA_DPL1    XREG( 0xDF84 )
#define  _NA_DPH1    XREG( 0xDF85 )
#define  X_U0CSR     XREG( 0xDF86 )
#define  _NA_PCON    XREG( 0xDF87 )

#define  _NA_TCON    XREG( 0xDF88 )
#define  X_P0IFG     XREG( 0xDF89 )
#define  X_P1IFG     XREG( 0xDF8A )
#define  X_P2IFG     XREG( 0xDF8B )
#define  X_PICTL     XREG( 0xDF8C )
#define  X_P1IEN     XREG( 0xDF8D )
#define  _NA_SFR8E   XREG( 0xDF8E )
#define  X_P0INP     XREG( 0xDF8F )

#define  _NA_P1      XREG( 0xDF90 )
#define  X_RFIM      XREG( 0xDF91 )
#define  _NA_DPS     XREG( 0xDF92 )
#define  X_MPAGE     XREG( 0xDF93 )
#define  X_T2CMP     XREG( 0xDF94 )
#define  X_ST0       XREG( 0xDF95 )
#define  X_ST1       XREG( 0xDF96 )
#define  X_ST2       XREG( 0xDF97 )

#define  _NA_S0CON   XREG( 0xDF98 )
#define  _X_SFR99    XREG( 0xDF99 )
#define  _NA_IEN2    XREG( 0xDF9A )
#define  _NA_S1CON   XREG( 0xDF9B )
#define  X_T2PEROF0  XREG( 0xDF9C )
#define  X_T2PEROF1  XREG( 0xDF9D )
#define  X_T2PEROF2  XREG( 0xDF9E )
#define  _NA_SFR9F   XREG( 0xDF9F )

#define  _NA_P2      XREG( 0xDFA0 )
#define  X_T2OF0     XREG( 0xDFA1 )
#define  X_T2OF1     XREG( 0xDFA2 )
#define  X_T2OF2     XREG( 0xDFA3 )
#define  X_T2CAPLPL  XREG( 0xDFA4 )
#define  X_T2CAPHPH  XREG( 0xDFA5 )
#define  X_T2TLD     XREG( 0xDFA6 )
#define  X_T2THD     XREG( 0xDFA7 )

#define  _NA_IEN0    XREG( 0xDFA8 )
#define  _NA_IP0     XREG( 0xDFA9 )
#define  _X_SFRAA    XREG( 0xDFAA )
#define  X_FWT       XREG( 0xDFAB )
#define  X_FADDRL    XREG( 0xDFAC )
#define  X_FADDRH    XREG( 0xDFAD )
#define  X_FCTL      XREG( 0xDFAE )
#define  X_FWDATA    XREG( 0xDFAF )

#define  _X_SFRB0    XREG( 0xDFB0 )
#define  X_ENCDI     XREG( 0xDFB1 )
#define  X_ENCDO     XREG( 0xDFB2 )
#define  X_ENCCS     XREG( 0xDFB3 )
#define  X_ADCCON1   XREG( 0xDFB4 )
#define  X_ADCCON2   XREG( 0xDFB5 )
#define  X_ADCCON3   XREG( 0xDFB6 )
#define  X_RCCTRL    XREG( 0xDFB7 )

#define  _NA_IEN1    XREG( 0xDFB8 )
#define  _NA_IP1     XREG( 0xDFB9 )
#define  X_ADCL      XREG( 0xDFBA )
#define  X_ADCH      XREG( 0xDFBB )
#define  X_RNDL      XREG( 0xDFBC )
#define  X_RNDH      XREG( 0xDFBD )
#define  X_SLEEP     XREG( 0xDFBE )
#define  _X_SFRBF    XREG( 0xDFBF )

#define  _NA_IRCON   XREG( 0xDFC0 )
#define  X_U0DBUF    XREG( 0xDFC1 )
#define  X_U0BAUD    XREG( 0xDFC2 )
#define  X_T2CNF     XREG( 0xDFC3 )
#define  X_U0UCR     XREG( 0xDFC4 )
#define  X_U0GCR     XREG( 0xDFC5 )
#define  X_CLKCON    XREG( 0xDFC6 )
#define  X_MEMCTR    XREG( 0xDFC7 )

#define  _X_SFRC8    XREG( 0xDFC8 )
#define  X_WDCTL     XREG( 0xDFC9 )
#define  X_T3CNT     XREG( 0xDFCA )
#define  X_T3CTL     XREG( 0xDFCB )
#define  X_T3CCTL0   XREG( 0xDFCC )
#define  X_T3CC0     XREG( 0xDFCD )
#define  X_T3CCTL1   XREG( 0xDFCE )
#define  X_T3CC1     XREG( 0xDFCF )

#define  _NA_PSW     XREG( 0xDFD0 )
#define  X_DMAIRQ    XREG( 0xDFD1 )
#define  X_DMA1CFGL  XREG( 0xDFD2 )
#define  X_DMA1CFGH  XREG( 0xDFD3 )
#define  X_DMA0CFGL  XREG( 0xDFD4 )
#define  X_DMA0CFGH  XREG( 0xDFD5 )
#define  X_DMAARM    XREG( 0xDFD6 )
#define  X_DMAREQ    XREG( 0xDFD7 )

#define  X_TIMIF     XREG( 0xDFD8 )
#define  X_RFD       XREG( 0xDFD9 )
#define  X_T1CC0L    XREG( 0xDFDA )
#define  X_T1CC0H    XREG( 0xDFDB )
#define  X_T1CC1L    XREG( 0xDFDC )
#define  X_T1CC1H    XREG( 0xDFDD )
#define  X_T1CC2L    XREG( 0xDFDE )
#define  X_T1CC2H    XREG( 0xDFDF )

#define  _NA_ACC     XREG( 0xDFE0 )
#define  X_RFST      XREG( 0xDFE1 )
#define  X_T1CNTL    XREG( 0xDFE2 )
#define  X_T1CNTH    XREG( 0xDFE3 )
#define  X_T1CTL     XREG( 0xDFE4 )
#define  X_T1CCTL0   XREG( 0xDFE5 )
#define  X_T1CCTL1   XREG( 0xDFE6 )
#define  X_T1CCTL2   XREG( 0xDFE7 )

#define  _NA_IRCON2  XREG( 0xDFE8 )
#define  X_RFIF      XREG( 0xDFE9 )
#define  X_T4CNT     XREG( 0xDFEA )
#define  X_T4CTL     XREG( 0xDFEB )
#define  X_T4CCTL0   XREG( 0xDFEC )
#define  X_T4CC0     XREG( 0xDFED )
#define  X_T4CCTL1   XREG( 0xDFEE )
#define  X_T4CC1     XREG( 0xDFEF )

#define  _NA_B       XREG( 0xDFF0 )
#define  X_PERCFG    XREG( 0xDFF1 )
#define  X_ADCCFG    XREG( 0xDFF2 )
#define  X_P0SEL     XREG( 0xDFF3 )
#define  X_P1SEL     XREG( 0xDFF4 )
#define  X_P2SEL     XREG( 0xDFF5 )
#define  X_P1INP     XREG( 0xDFF6 )
#define  X_P2INP     XREG( 0xDFF7 )

#define  X_U1CSR     XREG( 0xDFF8 )
#define  X_U1DBUF    XREG( 0xDFF9 )
#define  X_U1BAUD    XREG( 0xDFFA )
#define  X_U1UCR     XREG( 0xDFFB )
#define  X_U1GCR     XREG( 0xDFFC )
#define  X_P0DIR     XREG( 0xDFFD )
#define  X_P1DIR     XREG( 0xDFFE )
#define  X_P2DIR     XREG( 0xDFFF )

/* ------------------------------------------------------------------------------------------------
 */
#ifdef __IAR_SYSTEMS_ICC__
#pragma language=default
#endif

/**************************************************************************************************
 */
#endif