?? iocc1110.h
字號(hào):
/**************************************************************************************************
* - ioCC1110.h -
*
* Special header for the Chipcon CC1110 System on Chip.
*
**************************************************************************************************
*/
#ifndef IOCC1110_H
#define IOCC1110_H
/* ------------------------------------------------------------------------------------------------
* Compiler Abstraction
* ------------------------------------------------------------------------------------------------
*/
#ifdef __IAR_SYSTEMS_ICC__
#pragma language=extended
#define SFR(name,addr) __sfr __no_init volatile unsigned char name @ addr;
#define SFRBIT(name, addr, bit7, bit6, bit5, bit4, bit3, bit2, bit1, bit0) \
__sfr __no_init volatile union \
{ \
unsigned char name; \
struct { \
unsigned char bit0 : 1; \
unsigned char bit1 : 1; \
unsigned char bit2 : 1; \
unsigned char bit3 : 1; \
unsigned char bit4 : 1; \
unsigned char bit5 : 1; \
unsigned char bit6 : 1; \
unsigned char bit7 : 1; \
}; \
} @ addr;
#define SBIT(name,addr) /* not in use for IAR C Compiler */
#define XREG(addr) ((unsigned char volatile __xdata *) 0)[addr]
#define VECT(num,addr) addr
#elif defined __IAR_SYSTEMS_ASM__
#define SFR(name,addr) name DEFINE addr
#define SFRBIT(name, addr, bit7, bit6, bit5, bit4, bit3, bit2, bit1, bit0) name DEFINE addr
#define SBIT(name,addr) name DEFINE addr
#define XREG(addr) addr
#define VECT(num,addr) addr
/* IAR assembler uses some predefined registers. The following prevents name collisions. */
#define SP SPx
#define ACC ACCx
#define B Bx
#define PSW PSWx
#define CY CYx
#define AC ACx
#define F0 F0x
#define RS1 RS1x
#define RS0 RS0x
#define OV OVx
#define P Px
#elif defined __KEIL__
#define SFR(name,addr) sfr name = addr;
#define SFRBIT(name, addr, bit7, bit6, bit5, bit4, bit3, bit2, bit1, bit0) sfr name = addr;
#define SBIT(name,addr) sbit name = addr;
#define VECT(num,addr) num
#ifdef __C51__
#define XREG(addr) ((unsigned char volatile xdata *) 0)[addr]
#elif defined __AX51__ || defined __A51__
#define XREG(addr) addr
#else
#error "Unknown Keil compiler."
#endif
#else
#error "Unrecognized compiler."
#endif
/* ------------------------------------------------------------------------------------------------
* Interrupt Vectors
* ------------------------------------------------------------------------------------------------
*/
#define RFTXRX_VECTOR VECT( 0, 0x03 ) /* RF TX done / RX ready */
#define ADC_VECTOR VECT( 1, 0x0B ) /* ADC End of Conversion */
#define URX0_VECTOR VECT( 2, 0x13 ) /* USART0 RX Complete */
#define URX1_VECTOR VECT( 3, 0x1B ) /* USART1 RX Complete */
#define ENC_VECTOR VECT( 4, 0x23 ) /* AES Encryption/Decryption Complete */
#define ST_VECTOR VECT( 5, 0x2B ) /* Sleep Timer Compare */
#define P2INT_VECTOR VECT( 6, 0x33 ) /* Port 2 Inputs */
#define UTX0_VECTOR VECT( 7, 0x3B ) /* USART0 TX Complete */
#define DMA_VECTOR VECT( 8, 0x43 ) /* DMA Transfer Complete */
#define T1_VECTOR VECT( 9, 0x4B ) /* Timer 1 (16-bit) Capture/Compare/Overflow */
#define T2_VECTOR VECT( 10, 0x53 ) /* Timer 2 (MAC Timer) Overflow */
#define T3_VECTOR VECT( 11, 0x5B ) /* Timer 3 (8-bit) Capture/Compare/Overflow */
#define T4_VECTOR VECT( 12, 0x63 ) /* Timer 4 (8-bit) Capture/Compare/Overflow */
#define P0INT_VECTOR VECT( 13, 0x6B ) /* Port 0 Inputs */
#define UTX1_VECTOR VECT( 14, 0x73 ) /* USART1 TX Complete */
#define P1INT_VECTOR VECT( 15, 0x7B ) /* Port 1 Inputs */
#define RF_VECTOR VECT( 16, 0x83 ) /* RF General Interrupts */
#define WDT_VECTOR VECT( 17, 0x8B ) /* Watchdog Overflow in Timer Mode */
/* ------------------------------------------------------------------------------------------------
* Interrupt Alias
* ------------------------------------------------------------------------------------------------
*/
#define I2SRX_VECTOR URX1_VECTOR /* I2S RX Complete, alias for URX1_VECTOR */
#define I2STX_VECTOR UTX1_VECTOR /* I2S TX Complete, alias for UTX1_VECTOR */
/* ------------------------------------------------------------------------------------------------
* SFRs
* ------------------------------------------------------------------------------------------------
*/
/* Port 0 */
SFRBIT( P0 , 0x80, P0_7, P0_6, P0_5, P0_4, P0_3, P0_2, P0_1, P0_0 )
SFR( SP , 0x81 ) /* Stack Pointer */
SFR( DPL0 , 0x82 ) /* Data Pointer 0 Low Byte */
SFR( DPH0 , 0x83 ) /* Data Pointer 0 High Byte */
SFR( DPL1 , 0x84 ) /* Data Pointer 1 Low Byte */
SFR( DPH1 , 0x85 ) /* Data Pointer 1 High Byte */
SFR( U0CSR , 0x86 ) /* USART 0 Control and Status */
SFR( PCON , 0x87 ) /* Power Mode Control */
/* CPU Interrupt Flag 1 */
SFRBIT( TCON , 0x88, URX1IF, _TCON6, ADCIF, _TCON4, URX0IF, _TCON2, RFTXRXIF, _TCON0 )
SFR( P0IFG , 0x89 ) /* Port 0 Interrupt Status Flag */
SFR( P1IFG , 0x8A ) /* Port 1 Interrupt Status Flag */
SFR( P2IFG , 0x8B ) /* Port 2 Interrupt Status Flag */
SFR( PICTL , 0x8C ) /* Port Interrupt Control */
SFR( P1IEN , 0x8D ) /* Port 1 Interrupt Mask */
SFR( _SFR8E , 0x8E ) /* not used */
SFR( P0INP , 0x8F ) /* Port 0 Input Mode */
/* Port 1 */
SFRBIT( P1 , 0x90, P1_7, P1_6, P1_5, P1_4, P1_3, P1_2, P1_1, P1_0 )
SFR( RFIM , 0x91 ) /* RF Interrupt Mask */
SFR( DPS , 0x92 ) /* Data Pointer Select */
SFR( MPAGE , 0x93 ) /* Memory Page Select */
SFR( _SFR94 , 0x94 ) /* not used */
SFR( _SFR95 , 0x95 ) /* not used */
SFR( _SFR96 , 0x96 ) /* not used */
SFR( _SFR97 , 0x97 ) /* not used */
/* CPU Interrupt Flag 2 */
SFRBIT( S0CON , 0x98, _SOCON7, _SOCON6, _SOCON5, _SOCON4, _SOCON3, _SOCON2, ENCIF_1, ENCIF_0 )
SFR( _SFR99 , 0x99 ) /* not used */
SFR( IEN2 , 0x9A ) /* Interrupt Enable 2 */
SFR( S1CON , 0x9B ) /* CPU Interrupt Flag 3 */
SFR( T2CT , 0x9C ) /* Timer 2 Count */
SFR( T2PR , 0x9D ) /* Timer 2 Prescaler */
SFR( T2CTL , 0x9E ) /* Timer 2 Control */
SFR( _SFR9F , 0x9F ) /* not used */
/* Port 2 */
SFRBIT( P2 , 0xA0, _P2_7, _P2_6, _P2_5, P2_4, P2_3, P2_2, P2_1, P2_0 )
SFR( WORIRQ , 0xA1 ) /* Sleep Timer Interrupt Control */
SFR( WORCTRL , 0xA2 ) /* Sleep Timer Control */
SFR( WOREVT0 , 0xA3 ) /* Sleep Timer Event0 Timeout Low */
SFR( WOREVT1 , 0xA4 ) /* Sleep Timer Event0 Timeout High */
SFR( WORTIME0 , 0xA5 ) /* Sleep Timer Low Byte */
SFR( WORTIME1 , 0xA6 ) /* Sleep Timer High Byte */
SFR( _SFRA7 , 0xA7 ) /* not used */
/* Interrupt Enable 0 */
SFRBIT( IEN0 , 0xA8, EA, _IEN06, STIE, ENCIE, URX1IE, URX0IE, ADCIE, RFTXRXIE )
SFR( IP0 , 0xA9 ) /* Interrupt Priority 0 */
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