?? clock.vhd
字號:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY clock IS
PORT (set,date,clo,clk,rst : IN STD_LOGIC;
co1,co2,co3,co4,co5,co6 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
c1,c2,c3 :OUT STD_LOGIC);
END clock;
ARCHITECTURE behav OF clock IS
component trs38
PORT (clk : IN STD_LOGIC;
sec,smin,shour,sday,smon,scmin,schour : OUT STD_LOGIC);
end component;
component second
PORT (clk,rst,ce : IN STD_LOGIC;
co1,co2,co3,co4,co5,co6 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
end component;
component time
PORT (clk,min,rst,day,hour,mon : IN STD_LOGIC;
co1,co2,co3,co4,co5,co6,co7,co8,co9,co01 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
end component;
COMPONENT nosy
PORT(scmin,schour : IN STD_LOGIC;
co1,co2,co3,co4:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
SIGNAL c,sec,min,hour,day,mon,noce,ced,cecl,smin,shour,sday,smon,cmin,chour,scmin,schour :STD_LOGIC;
SIGNAL s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16,s17,s18,s19,s20 :STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL cnt : std_logic_vector(1 downto 0);
BEGIN
U1: trs38 PORT MAP(clk=>set,sec=>sec,smin=>min,shour=>hour,sday=>day,smon=>mon,scmin=>cmin,schour=>chour);
noce <=sec AND date; -- -清零信號，如果使能則不能清零，只有在暫停時才能。
cecl <=sec AND clo; --秒表使能
process(cecl)
begin
if rising_edge(cecl) then
cnt<=cnt+1;
end if;
end process;
c <= cnt(0);
process(clk)
begin
if rising_edge(clk) then
if c='1' then ced<='0';
else ced<=noce;
end if;
end if;
end process;
U2: second PORT MAP(clk=>clk,ce=>c,rst=>ced,co1=>s1,co2=>s2,co3=>s3,co4=>s4,co5=>s5,co6=>s6);
smin<=min and date;
shour<=hour and date;
sday<=day and date;
smon<=mon and date;
U3: time PORT MAP(clk=>clk,rst=>rst,min=>smin,day=>sday,hour=>shour,mon=>smon,co1=>s7,co2=>s8,co3=>s9,co4=>s10,co5=>s11,co6=>s12,co7=>s13,co8=>s14,co9=>s15,co01=>s16);
scmin <= cmin AND date;
schour<=chour AND date;
U4: nosy PORT MAP(scmin=>scmin,schour=>schour,co1=>s17,co2=>s18,co3=>s19,co4=>s20);
process(date,sec,day,mon)
begin
if sec='1' then
co1<=s1;
co2<=s2;
co3<=s3;
co4<=s4;
co5<=s5;
co6<=s6;
c1 <='0';
c2 <='0';
c3 <='0';
elsif min='1' or hour='1' THEN
co1<=s7;
co2<=s8;
co3<=s9;
co4<=s10;
co5<=s11;
co6<=s12;
c1 <='0';
c2 <=min;
c3 <=hour;
elsif clo='1' OR cmin='1' OR chour='1' THEN
co1<=s17;
co2<=s18;
co3<=s19;
co4<=s20;
co5<="0000";
co6<="0000";
c1 <=cmin;
c2 <=chour;
c3 <='1';
elsif date='1' or mon='1' or day='1' then
co1<=s13;
co2<=s14;
co3<="0000";
co4<="0000";
co5<=s15;
co6<=s16;
c1 <=day;
c2 <='0';
c3 <=mon;
else
co1<=s7;
co2<=s8;
co3<=s9;
co4<=s10;
co5<=s11;
co6<=s12;
c1 <='0';
c2 <='0';
c3 <='0';
end if;
end process;
end behav;
-----------------------======================--------------------------===============
-- =============譯碼器===============
--=====================================================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY trs38 IS
PORT (clk : IN STD_LOGIC;
sec,smin,shour,sday,smon,scmin,schour : OUT STD_LOGIC);
END trs38;
ARCHITECTURE behav OF trs38 IS
SIGNAL c : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
PROCESS (clk)
BEGIN
IF RISING_EDGE(clk) THEN
c <= c+1;
END IF;
END PROCESS;
PROCESS (c)
BEGIN
CASE c IS
WHEN "000" =>
sec <= '0';
smin <= '0';
shour<= '0';
sday <= '0';
smon <= '0';
scmin <='0';
schour<='0';
WHEN "001" =>
sec <= '1';
smin <= '0';
shour<= '0';
sday <= '0';
smon <= '0';
scmin <= '0';
schour<='0';
WHEN "010" =>
sec <= '0';
smin <= '1';
shour<= '0';
sday <= '0';
smon <= '0';
scmin <='0';
schour<='0';
WHEN "011" =>
sec <= '0';
smin <= '0';
shour<= '1';
sday <= '0';
smon <= '0';
scmin <='0';
schour<='0';
WHEN "100" =>
sec <= '0';
smin <= '0';
shour <= '0';
sday <= '1';
smon <= '0';
scmin <= '0';
schour <= '0';
WHEN "101" =>
sec <= '0';
smin <= '0';
shour<= '0';
sday <= '0';
smon <= '1';
scmin <='0';
schour<='0';
WHEN "110" =>
sec <= '0';
smin <= '0';
shour<= '0';
sday <= '0';
smon <= '0';
scmin <='1';
schour<='0';
WHEN OTHERS =>
sec <= '0';
smin <= '0';
shour<= '0';
sday <= '0';
smon <= '0';
scmin <='0';
schour<='1';
END CASE;
END PROCESS;
END behav;
------------------========================-------------------==================------------
-- =====================秒表=======================
--=========================================================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY second IS
PORT (clk,rst,ce : IN STD_LOGIC;
co1,co2,co3,co4,co5,co6 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END second;
ARCHITECTURE show OF second IS
component cnt100
PORT (ce,rst,clk : IN STD_LOGIC;
ca : OUT STD_LOGIC;
co1,co2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
end component;
component cnt60
PORT (ce,rst,clk : IN STD_LOGIC;
ca : OUT STD_LOGIC;
co1,co2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
end component;
component cnt60o
PORT (ce,rst,clk : IN STD_LOGIC;
co1,co2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
end component;
SIGNAL s1,s2,s3,s4,s5,s6 : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal c1,c2 : std_logic;
BEGIN
u1:cnt100 port map(ce=>ce,rst=>rst,clk=>clk,co1=>s1,co2=>s2,ca=>c1);
u2:cnt60 port map(ce=>ce,rst=>rst,clk=>c1,co1=>s3,co2=>s4,ca=>c2);
u3:cnt60o port map(ce=>ce,rst=>rst,clk=>c2,co1=>s5,co2=>s6);
co1<=s1;
co2<=s2;
co3<=s3;
co4<=s4;
co5<=s5;
co6<=s6;
end show;
---------------------==========================--------------------====================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt100 IS
PORT (ce,rst,clk : IN STD_LOGIC;
ca : OUT STD_LOGIC;
co1,co2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END cnt100;
ARCHITECTURE wav OF cnt100 IS
SIGNAL s1,s2 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c : STD_LOGIC;
BEGIN
PROCESS (clk,rst,ce)
BEGIN
IF rst = '1' THEN
s1 <= "0000";
s2 <= "0000";
ELSIF RISING_EDGE(clk) THEN
IF ce = '1' THEN
IF (s1 = 9) AND (s2 = 9) THEN
s1 <= "0000";
s2 <= "0000";
c <= '1';
ELSIF (s1 = 9) THEN
s1 <= "0000";
s2 <= s2 + 1;
c <='0';
ELSE s1 <= s1 + 1;
c <= '0';
END IF;
END IF;
END IF;
END PROCESS;
co1 <= s1;
co2 <= s2;
ca <= c;
END wav;
-----------------------------================================================-------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt60 IS
PORT (ce,rst,clk : IN STD_LOGIC;
ca : OUT STD_LOGIC;
co1,co2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END cnt60;
ARCHITECTURE wav OF cnt60 IS
SIGNAL s1,s2 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c : STD_LOGIC;
BEGIN
PROCESS (clk,rst,ce)
BEGIN
IF rst = '1' THEN
s1 <= "0000";
s2 <= "0000";
ELSIF RISING_EDGE(clk) THEN
IF ce = '1' THEN
IF (s1 = 9) AND (s2 = 5) THEN
s1 <= "0000";
s2 <= "0000";
c <= '1';
ELSIF (s1 = 9) THEN
s1 <= "0000";
s2 <= s2 + 1;
c <='0';
ELSE s1 <= s1 + 1;
c <= '0';
END IF;
END IF;
END IF;
END PROCESS;
co1 <= s1;
co2 <= s2;
ca <= c;
END wav;
-------------------=============================----------------------=================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt60o IS
PORT (ce,rst,clk : IN STD_LOGIC;
co1,co2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END cnt60o;
ARCHITECTURE wav OF cnt60o IS
SIGNAL s1,s2 : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS (clk,rst,ce)
BEGIN
IF rst = '1' THEN
s1 <= "0000";
s2 <= "0000";
ELSIF RISING_EDGE(clk) THEN
IF ce = '1' THEN
IF (s1 = 9) AND (s2 = 5) THEN
s1 <= "0000";
s2 <= "0000";
ELSIF (s1 = 9) THEN
s1 <= "0000";
s2 <= s2 + 1;
ELSE s1 <= s1 + 1;
END IF;
END IF;
END IF;
END PROCESS;
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