?? ml674001.h
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/**********************************************************************************/
/* */
/* Copyright (C) 2002 Oki Electric Industry Co., LTD. */
/* */
/* System Name : ML674001 series */
/* Module Name : Common definition include file for ML674001 series */
/* File Name : ML674001.h */
/* Revision : 01.00 */
/* Date : 2002/12/09 */
/* */
/**********************************************************************************/
#ifndef ML674001_H
#define ML674001_H
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------ uPLAT-7B core -----------------------------------*/
/*****************************************************/
/* interrupt control register */
/*****************************************************/
#define ICR_BASE (0x78000000) /* base address of interrupt control register */
#define IRQ (ICR_BASE+0x00) /* IRQ register (R,32,0x00000000) */
#define IRQS (ICR_BASE+0x04) /* IRQ soft register (RW,32,0x00000000) */
#define FIQ (ICR_BASE+0x08) /* FIQ register (R,32,0x00000000) */
#define FIQRAW (ICR_BASE+0x0C) /* FIQRAW status register (R,32,--)*/
#define FIQEN (ICR_BASE+0x10) /* FIQ enable register (RW,32,0x00000000)*/
#define IRN (ICR_BASE+0x14) /* IRQ number register (R,32,0x00000000)*/
#define CIL (ICR_BASE+0x18) /* current IRQ level register (RW,32,0x00000000)*/
#define ILC0 (ICR_BASE+0x20) /* IRQ level control register 0 (RW,32,0x00000000) */
#define ILC1 (ICR_BASE+0x24) /* IRQ level control register 1 (RW,32,0x00000000) */
#define CILCL (ICR_BASE+0x28) /* current IRQ level clear register (W,32,--) */
#define CILE (ICR_BASE+0x2C) /* current IRQ level encode register (R,32,0x00000000) */
/* bit field of IRQ register */
#define IRQ_nIR0 (0x00000001) /* nIR[0] */
#define IRQ_nIR1 (0x00000002) /* nIR[1] */
#define IRQ_nIR2 (0x00000004) /* nIR[2] */
#define IRQ_nIR3 (0x00000008) /* nIR[3] */
#define IRQ_nIR4 (0x00000010) /* nIR[4] */
#define IRQ_nIR5 (0x00000020) /* nIR[5] */
#define IRQ_nIR6 (0x00000040) /* nIR[6] */
#define IRQ_nIR7 (0x00000080) /* nIR[7] */
#define IRQ_nIR8 (0x00000100) /* nIR[8] */
#define IRQ_nIR9 (0x00000200) /* nIR[9] */
#define IRQ_nIR10 (0x00000400) /* nIR[10] */
#define IRQ_nIR11 (0x00000800) /* nIR[11] */
#define IRQ_nIR12 (0x00001000) /* nIR[12] */
#define IRQ_nIR13 (0x00002000) /* nIR[13] */
#define IRQ_nIR14 (0x00004000) /* nIR[14] */
#define IRQ_nIR15 (0x00008000) /* nIR[15] */
/* bit field of IRQS register */
#define IRQS_IRQS (0x00000002) /* IRQS bit */
/* bit field of FIQ register */
#define FIQ_FIQ (0x00000001) /* FIQ bit */
/* bit field of FIQRAW register */
#define FIQRAW_FIQRAW (0x00000001) /* FIQRAW bit */
/* bit field of FIQEN register */
#define FIQEN_FIQEN (0x00000001) /* FIQEN bit */
/* bit field of IRN register */
#define IRN_IRN (0x0000007F) /* IRN[6:0] */
/* bit field of CIL register */
#define CIL_INT_LV1 (0x00000002) /* interrupt level 1 */
#define CIL_INT_LV2 (0x00000004) /* interrupt level 2 */
#define CIL_INT_LV3 (0x00000008) /* interrupt level 3 */
#define CIL_INT_LV4 (0x00000010) /* interrupt level 4 */
#define CIL_INT_LV5 (0x00000020) /* interrupt level 5 */
#define CIL_INT_LV6 (0x00000040) /* interrupt level 6 */
#define CIL_INT_LV7 (0x00000080) /* interrupt level 7 */
/* bit field of ILC0 register */
#define ILC0_INT_LV1 (0x11111111) /* interrupt level 1 */
#define ILC0_INT_LV2 (0x22222222) /* interrupt level 2 */
#define ILC0_INT_LV3 (0x33333333) /* interrupt level 3 */
#define ILC0_INT_LV4 (0x44444444) /* interrupt level 4 */
#define ILC0_INT_LV5 (0x55555555) /* interrupt level 5 */
#define ILC0_INT_LV6 (0x66666666) /* interrupt level 6 */
#define ILC0_INT_LV7 (0x77777777) /* interrupt level 7 */
#define ILC0_ILR0 (0x00000007) /* nIR[0] */
#define ILC0_ILR1 (0x00000070) /* nIR[1],nIR[2],nIR[3] */
#define ILC0_ILR4 (0x00070000) /* nIR[4],nIR[5] */
#define ILC0_ILR6 (0x07000000) /* nIR[6],nIR[7] */
/* bit field of ILC1 register */
#define ILC1_INT_LV1 (0x11111111) /* interrupt level 1 */
#define ILC1_INT_LV2 (0x22222222) /* interrupt level 2 */
#define ILC1_INT_LV3 (0x33333333) /* interrupt level 3 */
#define ILC1_INT_LV4 (0x44444444) /* interrupt level 4 */
#define ILC1_INT_LV5 (0x55555555) /* interrupt level 5 */
#define ILC1_INT_LV6 (0x66666666) /* interrupt level 6 */
#define ILC1_INT_LV7 (0x77777777) /* interrupt level 7 */
#define ILC1_ILR8 (0x00000007) /* nIR[8] */
#define ILC1_ILR9 (0x00000070) /* nIR[9] */
#define ILC1_ILR10 (0x00000700) /* nIR[10] */
#define ILC1_ILR11 (0x00007000) /* nIR[11] */
#define ILC1_ILR12 (0x00070000) /* nIR[12] */
#define ILC1_ILR13 (0x00700000) /* nIR[13] */
#define ILC1_ILR14 (0x07000000) /* nIR[14] */
#define ILC1_ILR15 (0x70000000) /* nIR[15] */
/* bit field of CILCL register */
#define CILCL_CLEAR (0x00000001) /* most significant '1' bit of CIL is cleared */
/* bit field of CILE register */
#define CILE_CILE (0x00000007) /* CILE[2:0] */
/*****************************************************/
/* external memory control register */
/*****************************************************/
#define EMCR_BASE (0x78100000) /* base address */
#define BWC (EMCR_BASE+0x00) /* bus width control register (RW,32,0x00000008) */
#define ROMAC (EMCR_BASE+0x04) /* external ROM access control register (RW,32,0x00000007) */
#define RAMAC (EMCR_BASE+0x08) /* external SRAM access control register (RW,32,0x00000007) */
#define IO0AC (EMCR_BASE+0x0C) /* external IO0 access control register (RW,32,0x00000007) */
#define IO1AC (EMCR_BASE+0x10) /* external IO1 access control register (RW,32,0x00000007) */
/* bit field of BWC register */
#define BWC_ROMBW0 (0x00000000) /* ROM disable */
#define BWC_ROMBW16 (0x00000008) /* ROM 16bit */
#define BWC_RAMBW0 (0x00000000) /* RAM disable */
#define BWC_RAMBW16 (0x00000020) /* RAM 16bit */
#define BWC_IO0BW0 (0x00000000) /* IO0 disable */
#define BWC_IO0BW8 (0x00000040) /* IO0 8bit */
#define BWC_IO0BW16 (0x00000080) /* IO0 16 bit */
#define BWC_IO1BW0 (0x00000000) /* IO1 disable */
#define BWC_IO1BW8 (0x00000100) /* IO1 8bit */
#define BWC_IO1BW16 (0x00000200) /* IO1 16bit */
/* bit field of ROMAC register */
#define ROMAC_ROMTYPE (0x00000007) /* ROMTYPE[2:0] */
/* bit field of RAMAC register */
#define RAMAC_RAMTYPE (0x00000007) /* RAMTYPE[2:0] */
/* bit field of IO0AC register */
#define IO0AC_IO0TYPE (0x00000007) /* IO0TYPE[2:0] */
/* bit field of IO1AC register */
#define IO1AC_IO1TYPE (0x00000007) /* IO1TYPE[2:0] */
/*****************************************************/
/* system control register */
/*****************************************************/
#define SCR_BASE (0xB8000000) /* base address */
#define CLKSTP (SCR_BASE+0x04) /* clock stop register (W,32,0x00000000) */
#define CGBCNT0 (SCR_BASE+0x08) /* clock(CGB) control register 0 (RW,32,0x00000000) */
#define CKWT (SCR_BASE+0x0C) /* clock wait register (RW,32,0x0000000B) */
#define RMPCON (SCR_BASE+0x10) /* remap control register (RW,32,0x00000000) */
/* bit field of CLKSTP register */
#define CLKSTP_SIO (0x00000001) /* SIO HALT */
#define CLKSTP_TIC (0x00000002) /* TIC HALT */
#define CLKSTP_HALT (0x00000004) /* CPU group HALT */
#define CLKSTP_STBY (0x000000F0) /* STANDBY */
/* bit field of CGBCNT0 register */
#define CGBCNT0_HCLK1 (0x00000000) /* HCLK 1 dividing */
#define CGBCNT0_HCLK2 (0x00000001) /* HCLK 2 dividing */
#define CGBCNT0_HCLK4 (0x00000002) /* HCLK 4 dividing */
#define CGBCNT0_HCLK8 (0x00000003) /* HCLK 8 dividing */
#define CGBCNT0_HCLK16 (0x00000004) /* HCLK 16 dividing */
#define CGBCNT0_CCLK1 (0x00000000) /* CCLK 1 dividing */
#define CGBCNT0_CCLK2 (0x00000010) /* CCLK 2 dividing */
#define CGBCNT0_CCLK4 (0x00000020) /* CCLK 4 dividing */
#define CGBCNT0_CCLK8 (0x00000030) /* CCLK 8 dividing */
#define CGBCNT0_CCLK16 (0x00000040) /* CCLK 16 dividing */
/* bit field of RMPCON register */
#define RMPCON_ENABLE (0x00000008) /* remap enabled */
#define RMPCON_DISABLE (0x00000000) /* remap disabled */
#define RMPCON_AHB (0x00000002) /* device space is AHB bus*/
#define RMPCON_EXT (0x00000000) /* device space is external bus */
#define RMPCON_DRAM (0x00000001) /* memory type is DRAM */
#define RMPCON_SRAM (0x00000000) /* memory type is SRAM */
#define RMPCON_IRAM (0x00000004) /* memory type is internal RAM */
/*****************************************************/
/* system timer control register */
/*****************************************************/
#define STCR_BASE (0xB8001000) /* base address */
#define TMEN (STCR_BASE+0x04) /* timer enable register (RW,16,0x0000) */
#define TMRLR (STCR_BASE+0x08) /* timer reload register (RW,16,0x0000) */
#define TMOVF (STCR_BASE+0x10) /* overflow register (RW,16,0x0000) */
/* bit field of TMEN register */
#define TMEN_TCEN (0x0001) /* timer enabled */
/* bit field of TMOVF register */
#define TMOVF_OVF (0x0001) /* overflow generated */
/*****************************************************/
/* ASIO control register */
/*****************************************************/
#define SC_BASE (0xB8002000) /* base address */
#define SIOBUF (SC_BASE+0x00) /* transmiting/receiving buffer register (RW,16,0x0000) */
#define SIOSTA (SC_BASE+0x04) /* SIO status register (RW,16,0x0000) */
#define SIOCON (SC_BASE+0x08) /* SIO control register (RW,16,0x0000) */
#define SIOBCN (SC_BASE+0x0C) /* baud rate control register (RW,16,0x0000) */
#define SIOBT (SC_BASE+0x14) /* baud rate timer register (RW,16,0x0000) */
#define SIOTCN (SC_BASE+0x18) /* SIO test control register (RW,16,0x0000) */
/* bit field of SIOBUF register */
#define SIOBUF_SIOBUF (0x00FF) /* SIOBUF[7:0] */
/* bit field of SIOSTA register */
#define SIOSTA_FERR (0x0001) /* framing error */
#define SIOSTA_OERR (0x0002) /* overrun error */
#define SIOSTA_PERR (0x0004) /* parity error */
#define SIOSTA_RVIRQ (0x0010) /* receive ready */
#define SIOSTA_TRIRQ (0x0020) /* transmit ready */
/* bit field of SIOCON register */
#define SIOCON_LN7 (0x0001) /* data length : 7bit */
#define SIOCON_LN8 (0x0000) /* data length : 8bit */
#define SIOCON_PEN (0x0002) /* parity enabled */
#define SIOCON_PDIS (0x0000) /* parity disabled */
#define SIOCON_EVN (0x0004) /* even parity */
#define SIOCON_ODD (0x0000) /* odd parity */
#define SIOCON_TSTB1 (0x0008) /* stop bit : 1 */
#define SIOCON_TSTB2 (0x0000) /* stop bit : 2 */
/* bit field of SIOBCN register */
#define SIOBCN_BGRUN (0x0010) /* count start */
/* bit field of SIOBT register */
#define SIOBT_SIOBT (0x00FF) /* SIOBT[7:0] */
/* bit field of SIOTCN register */
#define SIOTCN_MFERR (0x0001) /* generate framin error */
#define SIOTCN_MPERR (0x0002) /* generate parity error */
#define SIOTCN_LBTST (0x0080) /* loop back test */
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