/*---------------------------------- ML674001 ------------------------------------*/
/*****************************************************/
/*    timer control register                         */
/*****************************************************/
#define TCR_BASE    (0xB7F00000)    /* base address */
#define TIMECNTL0   (TCR_BASE+0x00) /* timer0 control register (RW,16,0x0000) */
#define TIMEBASE0   (TCR_BASE+0x04) /* timer0 base register (RW,16,0x0000) */
#define TIMECNT0    (TCR_BASE+0x08) /* timer0 counter register (R,16,0x0000) */
#define TIMECMP0    (TCR_BASE+0x0C) /* timer0 compare register (RW,16,0xFFFF) */
#define TIMESTAT0   (TCR_BASE+0x10) /* timer0 status register (RW,16,0x0000) */
#define TIMECNTL1   (TCR_BASE+0x20) /* timer1 control register (RW,16,0x0000) */
#define TIMEBASE1   (TCR_BASE+0x24) /* timer1 base register (RW,16,0x0000) */
#define TIMECNT1    (TCR_BASE+0x28) /* timer1 counter register (R,16,0x0000) */
#define TIMECMP1    (TCR_BASE+0x2C) /* timer1 compare register (RW,16,0xFFFF) */
#define TIMESTAT1   (TCR_BASE+0x30) /* timer1 status register (RW,16,0x0000) */
#define TIMECNTL2   (TCR_BASE+0x40) /* timer2 control register (RW,16,0x0000) */
#define TIMEBASE2   (TCR_BASE+0x44) /* timer2 base register (RW,16,0x0000) */
#define TIMECNT2    (TCR_BASE+0x48) /* timer2 counter register (R,16,0x0000) */
#define TIMECMP2    (TCR_BASE+0x4C) /* timer2 compare register (RW,16,0xFFFF) */
#define TIMESTAT2   (TCR_BASE+0x50) /* timer2 status register (RW,16,0x0000) */
#define TIMECNTL3   (TCR_BASE+0x60) /* timer3 control register (RW,16,0x0000) */
#define TIMEBASE3   (TCR_BASE+0x64) /* timer3 base register (RW,16,0x0000) */
#define TIMECNT3    (TCR_BASE+0x68) /* timer3 counter register (R,16,0x0000) */
#define TIMECMP3    (TCR_BASE+0x6C) /* timer3 compare register (RW,16,0xFFFF) */
#define TIMESTAT3   (TCR_BASE+0x70) /* timer3 status register (RW,16,0x0000) */
#define TIMECNTL4   (TCR_BASE+0x80) /* timer4 control register (RW,16,0x0000) */
#define TIMEBASE4   (TCR_BASE+0x84) /* timer4 base register (RW,16,0x0000) */
#define TIMECNT4    (TCR_BASE+0x88) /* timer4 counter register (R,16,0x0000) */
#define TIMECMP4    (TCR_BASE+0x8C) /* timer4 compare register (RW,16,0xFFFF) */
#define TIMESTAT4   (TCR_BASE+0x90) /* timer4 status register (RW,16,0x0000) */
#define TIMECNTL5   (TCR_BASE+0xA0) /* timer5 control register (RW,16,0x0000) */
#define TIMEBASE5   (TCR_BASE+0xA4) /* timer5 base register (RW,16,0x0000) */
#define TIMECNT5    (TCR_BASE+0xA8) /* timer5 counter register (R,16,0x0000) */
#define TIMECMP5    (TCR_BASE+0xAC) /* timer5 compare register (RW,16,0xFFFF) */
#define TIMESTAT5   (TCR_BASE+0xB0) /* timer5 status register (RW,16,0x0000) */

/* bit field of TIMECNTL0-5 register */
#define TIMECNTL_CLK    (0x0000)    /* CPUCLK */
#define TIMECNTL_CLK2   (0x0020)    /* CPUCLK/2 */
#define TIMECNTL_CLK4   (0x0040)    /* CPUCLK/4 */
#define TIMECNTL_CLK8   (0x0060)    /* CPUCLK/8 */
#define TIMECNTL_CLK16  (0x0080)    /* CPUCLK/16 */
#define TIMECNTL_CLK32  (0x00A0)    /* CPUCLK/32 */
#define TIMECNTL_IE     (0x0010)    /* enable interrupt */
#define TIMECNTL_START  (0x0008)    /* timer start */
#define TIMECNTL_OS     (0x0001)    /* one shot timer */
#define TIMECNTL_INT    (0x0000)    /* interval timer */

/* bit field of TIMESTAT0-5 register */
#define TIMESTAT_STATUS (0x0001)    /* status bit */

/*****************************************************/
/*    Watch Dog Timer control register               */
/*****************************************************/
#define WDT_BASE    (0xB7E00000)    /* base address */
#define WDTCON      (WDT_BASE+0x00) /* Watch Dog Timer control register (W,8,--) */
#define WDTBCON     (WDT_BASE+0x04) /* time base counter control register (RW,8,0x00) */
#define WDSTAT      (WDT_BASE+0x14) /* Watch Dog Timer status register (RW,8,0x00) */

/* bit field of WDTCON */
#define WDTCON_0xC3 (0xC3)  /* 0xC3 */
#define WDTCON_0x3C (0x3C)  /* 0x3C */

/* bit field of WDTBCON */
#define WDTBCON_CLK32   (0x00)  /* CPUCLK/32 */
#define WDTBCON_CLK64   (0x01)  /* CPUCLK/64 */
#define WDTBCON_CLK128  (0x02)  /* CPUCLK/128 */
#define WDTBCON_CLK256  (0x03)  /* CPUCLK/256 */
#define WDTBCON_WDTM    (0x00)  /* WDT mode */
#define WDTBCON_ITM     (0x08)  /* interval timer mode */
#define WDTBCON_ITDIS   (0x00)  /* disable interval timer */
#define WDTBCON_ITEN    (0x10)  /* enable interval timer */
#define WDTBCON_INT     (0x00)  /* generate interrupt */
#define WDTBCON_RESET   (0x40)  /* system reset */
#define WDTBCON_WDHLT   (0x80)  /* HALT */
#define WDTBCON_WE      (0x5A)  /* enable writing to this register */

/* bit field of WDTSTAT */
#define WDSTAT_RSTWDT   (0x01)  /* reset by WDT */
#define WDSTAT_RSTPWON  (0x00)  /* reset by power on */
#define WDSTAT_WDTIST   (0x10)  /* WDT interrupt */
#define WDSTAT_IVTIST   (0x20)  /* IVT interrupt */


/*****************************************************/
/*    UART control register                          */
/*****************************************************/
#define UCR_BASE    (0xB7B00000)    /* base address */
#define UARTRBR     (UCR_BASE+0x00) /* receiver buffer register (R,8,--) */
#define UARTTHR     (UCR_BASE+0x00) /* transmitter buffer register (R,8--) */
#define UARTIER     (UCR_BASE+0x04) /* interrupt enable register (RW,8,0x00) */
#define UARTIIR     (UCR_BASE+0x08) /* interrupt identification (R,8,0x01) */
#define UARTFCR     (UCR_BASE+0x08) /* FIFO control register (W,8,0x00) */
#define UARTLCR     (UCR_BASE+0x0C) /* line control register (RW,8,0x00) */
#define UARTMCR     (UCR_BASE+0x10) /* modem control register (RW,8,0x00) */
#define UARTLSR     (UCR_BASE+0x14) /* line status register (RW,8,0x60) */
#define UARTMSR     (UCR_BASE+0x18) /* modem status register (RW,8,--) */
#define UARTSCR     (UCR_BASE+0x1C) /* scratchpad register (RW,8,--) */
#define UARTDLL     (UCR_BASE+0x00) /* divisor latch(LSB) (RW,8,0x00) */
#define UARTDLM     (UCR_BASE+0x04) /* divisor latch(MSB) (RW,8,0x00) */

/* bit field of UARTRBR register */
#define UARTRBR_RBR (0xFF)  /* RBR[7:0] */

/* bit field of UARTTHR register */
#define UARTTHR_THR (0xFF)  /* THR[7:0] */

/* bit field of UARTIER register */
#define UARTIER_ERBF    (0x01)  /* enable received data available interrupt */
#define UARTIER_ETBEF   (0x02)  /* enable transmitter holding register empty interrupt */
#define UARTIER_ELSI    (0x04)  /* enable receiver line status interrupt */
#define UARTIER_EDSI    (0x08)  /* enable modem status interrupt */

/* bit field of UARTIIR register */
#define UARTIIR_IP      (0x01)  /* interrupt generated */
#define UARTIIR_LINE    (0x06)  /* receiver line status interrupt */
#define UARTIIR_RCV     (0x04)  /* receiver interrupt */
#define UARTIIR_TO      (0x0C)  /* time out interrupt */
#define UARTIIR_TRA     (0x02)  /* transmitter interrupt */
#define UARTIIR_FM      (0xC0)  /* FIFO mode */

/* bit field of UARTFCR register */
#define UARTFCR_FE      (0x01)  /* FIFO enable */
#define UARTFCR_FD      (0x00)  /* FIFO disable */
#define UARTFCR_RFCLR   (0x02)  /* receiver FIFO clear */
#define UARTFCR_TFCLR   (0x04)  /* transmitter FIFO clear */
#define UARTFCR_RFLV1   (0x00)  /* RCVR FIFO interrupt trigger level : 1byte */
#define UARTFCR_RFLV4   (0x40)  /* RCVR FIFO interrupt trigger level : 4byte */
#define UARTFCR_RFLV8   (0x80)  /* RCVR FIFO interrupt trigger level : 8byte */
#define UARTFCR_RFLV14  (0xC0)  /* RCVR FIFO interrupt trigger level : 14byte */

/* bit field of UARTLCR register */
#define UARTLCR_LEN5    (0x00)  /* data length : 5bit */
#define UARTLCR_LEN6    (0x01)  /* data length : 6bit */
#define UARTLCR_LEN7    (0x02)  /* data length : 7bit */
#define UARTLCR_LEN8    (0x03)  /* data length : 8bit */
#define UARTLCR_STB1    (0x00)  /* stop bit : 1 */
#define UARTLCR_STB2    (0x04)  /* stop bit : 2(data length 6-8) */
#define UARTLCR_STB1_5  (0x04)  /* stop bit : 1.5(data length 5) */
#define UARTLCR_PEN     (0x08)  /* parity enabled */
#define UARTLCR_PDIS    (0x00)  /* parity disabled */
#define UARTLCR_EVN     (0x10)  /* even parity */
#define UARTLCR_ODD     (0x00)  /* odd parity */
#define UARTLCR_SP      (0x20)  /* stick parity */
#define UARTLCR_BRK     (0x40)  /* break delivery */
#define UARTLCR_DLAB    (0x80)  /* devisor latch access bit */

/* bit field of UARTMCR register */
#define UARTMCR_DTR     (0x01)  /* data terminal ready */
#define UARTMCR_RTS     (0x02)  /* request to send */
#define UARTMCR_LOOP    (0x10)  /* loopback */

/* bit field of UARTLSR register */
#define UARTLSR_DR      (0x01)  /* data ready */
#define UARTLSR_OE      (0x02)  /* overrun error */
#define UARTLSR_PE      (0x04)  /* parity error */
#define UARTLSR_FE      (0x08)  /* framing error */
#define UARTLSR_BI      (0x10)  /* break interrupt */
#define UARTLSR_THRE    (0x20)  /* transmitter holding register empty */
#define UARTLSR_TEMT    (0x40)  /* transmitter empty */
#define UARTLSR_ERF     (0x80)  /* receiver FIFO error */

/* bit field of UARTMSR register */
#define UARTMSR_DCTS    (0x01)  /* delta clear to send */
#define UARTMSR_DDSR    (0x02)  /* delta data set ready */
#define UARTMSR_TERI    (0x04)  /* trailing edge of ring endicator */
#define UARTMSR_DDCD    (0x08)  /* delta data carrer detect */
#define UARTMSR_CTS     (0x10)  /* clear to send */
#define UARTMSR_DSR     (0x20)  /* data set ready */
#define UARTMSR_RI      (0x40)  /* ring indicator */
#define UARTMSR_DCD     (0x80)  /* data carrer detect */

/* bit field of UARTSCR register */
#define UARTSCR_SCR (0xFF)  /* SCR[7:0] */

/* bit field of UARTDLL register */
#define UARTDLL_DLL (0xFF)  /* DLL[7:0](=DL[7:0]) */

/* bit field of UARTDLM register */
#define UARTDLM_DLM (0xFF)  /* DLM[7:0](=DL[15:8]) */


/*****************************************************/
/*    PWM control register                           */
/*****************************************************/
#define PWM_BASE    (0xB7D00000)    /* base address */
#define PWR0        (PWM_BASE+0x00) /* PWM register 0 (RW,16,0x0000) */
#define PWCY0       (PWM_BASE+0x04) /* PWM cycle register 0 (RW,16,0x0000) */
#define PWC0        (PWM_BASE+0x08) /* PWM counter 0 (RW,16,0x0000) */
#define PWCON0      (PWM_BASE+0x0C) /* PWM contrlo register 0 (RW,16,0x0000) */
#define PWR1        (PWM_BASE+0x20) /* PWM register 1 (RW,16,0x0000) */
#define PWCY1       (PWM_BASE+0x24) /* PWM cycle register 1 (RW,16,0x0000) */
#define PWC1        (PWM_BASE+0x28) /* PWM counter 1 (RW,16,0x0000) */
#define PWCON1      (PWM_BASE+0x2C) /* PWM contrlo register 1 (RW,16,0x0000) */
#define PWINTSTS    (PWM_BASE+0x3C) /* PWM interrupt status register (RW,16,0x0000) */

/* bit field of PWCON0,1 register */
#define PWCON_PWR   (0x0001)    /* enable PWC */
#define PWCON_CLK1  (0x0000)    /* 1/1 CPUCLK */
#define PWCON_CLK4  (0x0002)    /* 1/4 CPUCLK */
#define PWCON_CLK16 (0x0004)    /* 1/16 CPUCLK */
#define PWCON_CLK32 (0x0006)    /* 1/32 CPUCLK */
#define PWCON_INTIE (0x0040)    /* enable interrupt */
#define PWCON_PWCOV (0x0080)    

/* bit field of PWINTSTS register */
#define PWINTSTS_INT1S      (0x0200)    /* CH1 interrupt generated */
#define PWINTSTS_INT0S      (0x0100)    /* CH0 interrupt generated */
#define PWINTSTS_INT1CLR    (0x0002)    /* CH1 interrupt clear */
#define PWINTSTS_INT0CLR    (0x0001)    /* CH0 interrupt clear */


/*****************************************************/
/*    port control register                           */
/*****************************************************/
#define PCR_BASE    (0xB7A01000)    /* base address */
#define GPPOA       (PCR_BASE+0x00) /* port A output register (RW,16,--) */
#define GPPIA       (PCR_BASE+0x04) /* port A input register (R,16,--)*/
#define GPPMA       (PCR_BASE+0x08) /* port A Mode register (RW,16,0x0000) */
#define GPIEA       (PCR_BASE+0x0C) /* port A interrupt enable (RW,16,0x0000) */
#define GPIPA       (PCR_BASE+0x10) /* port A interrupt Polarity (RW,16,0x0000) */
#define GPISA       (PCR_BASE+0x14) /* port A interrupt Status (RW,16,0x0000) */

#define GPPOB       (PCR_BASE+0x20) /* port B Output register (RW,16,--) */
#define GPPIB       (PCR_BASE+0x24) /* port B Input register (RW,16,--) */
#define GPPMB       (PCR_BASE+0x28) /* port B Mode register (RW,16,0x0000) */
#define GPIEB       (PCR_BASE+0x2C) /* port B interrupt enable (RW,16,0x0000) */
#define GPIPB       (PCR_BASE+0x30) /* port B interrupt Polarity (RW,16,0x0000) */
#define GPISB       (PCR_BASE+0x34) /* port B interrupt Status (RW,16,0x0000) */

#define GPPOC       (PCR_BASE+0x40) /* port C Output register (RW,16,--) */
#define GPPIC       (PCR_BASE+0x44) /* port C Input register (RW,16,--) */
#define GPPMC       (PCR_BASE+0x48) /* port C Mode register (RW,16,0x0000) */
#define GPIEC       (PCR_BASE+0x4C) /* port C interrupt enable (RW,16,0x0000) */
#define GPIPC       (PCR_BASE+0x50) /* port C interrupt Polarity (RW,16,0x0000) */
#define GPISC       (PCR_BASE+0x54) /* port C interrupt Status (RW,16,0x0000) */

#define GPPOD       (PCR_BASE+0x60) /* port D Output register (RW,16,--) */
#define GPPID       (PCR_BASE+0x64) /* port D Input register (RW,16,--) */
#define GPPMD       (PCR_BASE+0x68) /* port D Mode register (RW,16,0x0000) */
#define GPIED       (PCR_BASE+0x6C) /* port D interrupt enable (RW,16,0x0000) */