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--D1L71 is prog_ram:prog_ram|reduce_or~411 at LC_X25_Y24_N1
--operation mode is normal

D1L71 = B1_ram_addr[0] & B1_ram_addr[2] & (B1_ram_addr[3] $ !B1_ram_addr[1]) # !B1_ram_addr[0] & !B1_ram_addr[2] & B1_ram_addr[3] & !B1_ram_addr[1];


--D1L81 is prog_ram:prog_ram|reduce_or~412 at LC_X25_Y24_N4
--operation mode is normal

D1L81 = B1_ram_addr[4] & D1L61 # !B1_ram_addr[4] & (D1L71);


--D1_instruction[1] is prog_ram:prog_ram|instruction[1] at LC_X30_Y26_N0
--operation mode is normal

D1_instruction[1] = GLOBAL(D1L51) & D1_instruction[1] # !GLOBAL(D1L51) & (D1L81);

--B1_mem_read_addr[1] is cpu:cpu|mem_read_addr[1] at LC_X30_Y26_N0
--operation mode is normal

B1_mem_read_addr[1] = DFFEAS(D1_instruction[1], GLOBAL(clock), VCC, , B1L001, , , , );


--D1L91 is prog_ram:prog_ram|reduce_or~413 at LC_X25_Y24_N7
--operation mode is normal

D1L91 = B1_ram_addr[3] & B1_ram_addr[1] & (B1_ram_addr[0] $ B1_ram_addr[2]);


--D1L02 is prog_ram:prog_ram|reduce_or~414 at LC_X25_Y24_N5
--operation mode is normal

D1L02 = B1_ram_addr[4] & (!D1L61) # !B1_ram_addr[4] & D1L91;


--D1_instruction[2] is prog_ram:prog_ram|instruction[2] at LC_X28_Y25_N5
--operation mode is normal

D1_instruction[2] = GLOBAL(D1L51) & (D1_instruction[2]) # !GLOBAL(D1L51) & D1L02;

--B1_mem_read_addr[2] is cpu:cpu|mem_read_addr[2] at LC_X28_Y25_N5
--operation mode is normal

B1_mem_read_addr[2] = DFFEAS(D1_instruction[2], GLOBAL(clock), VCC, , B1L001, , , , );


--D1L12 is prog_ram:prog_ram|reduce_or~415 at LC_X24_Y24_N8
--operation mode is normal

D1L12 = B1_ram_addr[3] & (!B1_ram_addr[2] # !B1_ram_addr[1] # !B1_ram_addr[0]) # !B1_ram_addr[3] & (B1_ram_addr[1] # B1_ram_addr[2]);


--D1L22 is prog_ram:prog_ram|reduce_or~416 at LC_X24_Y24_N5
--operation mode is normal

D1L22 = B1_ram_addr[4] & (!D1L21 # !B1_ram_addr[0]) # !B1_ram_addr[4] & (D1L12);


--D1_instruction[4] is prog_ram:prog_ram|instruction[4] at LC_X31_Y27_N9
--operation mode is normal

D1_instruction[4] = GLOBAL(D1L51) & D1_instruction[4] # !GLOBAL(D1L51) & (D1L22);


--D1_instruction[5] is prog_ram:prog_ram|instruction[5] at LC_X31_Y27_N5
--operation mode is normal

D1_instruction[5] = GLOBAL(D1L51) & D1_instruction[5] # !GLOBAL(D1L51) & (!D1L61 & B1_ram_addr[4]);


--D1L32 is prog_ram:prog_ram|reduce_or~417 at LC_X25_Y24_N2
--operation mode is normal

D1L32 = B1_ram_addr[0] & (B1_ram_addr[2] $ (B1_ram_addr[3] # B1_ram_addr[1])) # !B1_ram_addr[0] & (B1_ram_addr[3] # B1_ram_addr[2] & !B1_ram_addr[1]);


--D1_instruction[8] is prog_ram:prog_ram|instruction[8] at LC_X29_Y24_N8
--operation mode is normal

D1_instruction[8] = GLOBAL(D1L51) & D1_instruction[8] # !GLOBAL(D1L51) & (!B1_ram_addr[4] & D1L32);


--D1L42 is prog_ram:prog_ram|reduce_or~418 at LC_X25_Y24_N9
--operation mode is normal

D1L42 = B1_ram_addr[0] & (B1_ram_addr[3] & !B1_ram_addr[1]) # !B1_ram_addr[0] & B1_ram_addr[1] & (B1_ram_addr[2] $ B1_ram_addr[3]);


--D1_instruction[9] is prog_ram:prog_ram|instruction[9] at LC_X29_Y24_N7
--operation mode is normal

D1_instruction[9] = GLOBAL(D1L51) & (D1_instruction[9]) # !GLOBAL(D1L51) & D1L42 & !B1_ram_addr[4];


--D1L52 is prog_ram:prog_ram|reduce_or~419 at LC_X25_Y24_N0
--operation mode is normal

D1L52 = B1_ram_addr[0] & B1_ram_addr[2] & (B1_ram_addr[3] $ B1_ram_addr[1]) # !B1_ram_addr[0] & (B1_ram_addr[2] & !B1_ram_addr[3] & !B1_ram_addr[1] # !B1_ram_addr[2] & B1_ram_addr[3] & B1_ram_addr[1]);


--D1_instruction[10] is prog_ram:prog_ram|instruction[10] at LC_X29_Y24_N3
--operation mode is normal

D1_instruction[10] = GLOBAL(D1L51) & (D1_instruction[10]) # !GLOBAL(D1L51) & D1L52 & !B1_ram_addr[4];


--D1L62 is prog_ram:prog_ram|reduce_or~420 at LC_X23_Y24_N2
--operation mode is normal

D1L62 = B1_ram_addr[1] & (B1_ram_addr[3] $ (!B1_ram_addr[2] & !B1_ram_addr[0])) # !B1_ram_addr[1] & (B1_ram_addr[0] & (!B1_ram_addr[3]) # !B1_ram_addr[0] & !B1_ram_addr[2] & B1_ram_addr[3]);


--D1_instruction[11] is prog_ram:prog_ram|instruction[11] at LC_X29_Y24_N2
--operation mode is normal

D1_instruction[11] = GLOBAL(D1L51) & D1_instruction[11] # !GLOBAL(D1L51) & (D1L62 # B1_ram_addr[4]);


--B1L21 is cpu:cpu|Mux~128 at LC_X31_Y27_N6
--operation mode is normal

B1L21 = D1_instruction[1] & (D1_instruction[0]) # !D1_instruction[1] & (D1_instruction[0] & (B1_r[1][0]) # !D1_instruction[0] & B1_r[0][0]);


--B1L31 is cpu:cpu|Mux~129 at LC_X31_Y27_N4
--operation mode is normal

B1L31 = D1_instruction[1] & (B1L21 & (B1_r[3][0]) # !B1L21 & B1_r[2][0]) # !D1_instruction[1] & B1L21;


--G1_decoder_node[0][0] is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|decoder_node[0][0] at LC_X30_Y25_N1
--operation mode is normal

G1_decoder_node[0][0] = LCELL(B1L9 & (B1L31));


--C1_c[0] is memory:memory|c[0] at LC_X28_Y27_N6
--operation mode is normal

C1_c[0]_lut_out = GND;
C1_c[0] = DFFEAS(C1_c[0]_lut_out, GLOBAL(clock), VCC, , C1L32, B1_data_in[0], , , VCC);


--C1_d[0] is memory:memory|d[0] at LC_X28_Y26_N9
--operation mode is normal

C1_d[0]_lut_out = GND;
C1_d[0] = DFFEAS(C1_d[0]_lut_out, GLOBAL(clock), VCC, , C1L92, B1_data_in[0], , , VCC);


--C1_a[0] is memory:memory|a[0] at LC_X28_Y26_N8
--operation mode is normal

C1_a[0]_lut_out = GND;
C1_a[0] = DFFEAS(C1_a[0]_lut_out, GLOBAL(clock), GLOBAL(rst), , C1L2, B1_data_in[0], , , VCC);


--C1L3 is memory:memory|Select~236 at LC_X27_Y26_N2
--operation mode is normal

C1_b[0]_qfbk = C1_b[0];
C1L3 = B1_mem_read_addr[0] & (C1_b[0]_qfbk # B1_mem_read_addr[2]) # !B1_mem_read_addr[0] & C1_a[0] & (!B1_mem_read_addr[2]);

--C1_b[0] is memory:memory|b[0] at LC_X27_Y26_N2
--operation mode is normal

C1_b[0] = DFFEAS(C1L3, GLOBAL(clock), GLOBAL(rst), , C1L1, B1_data_in[0], , , VCC);


--C1_f[0] is memory:memory|f[0] at LC_X27_Y25_N2
--operation mode is normal

C1_f[0]_lut_out = GND;
C1_f[0] = DFFEAS(C1_f[0]_lut_out, GLOBAL(clock), VCC, , C1L74, B1_data_in[0], , , VCC);


--C1L4 is memory:memory|Select~237 at LC_X27_Y26_N6
--operation mode is normal

C1_e[0]_qfbk = C1_e[0];
C1L4 = C1L3 & (C1_f[0] # !B1_mem_read_addr[2]) # !C1L3 & (C1_e[0]_qfbk & B1_mem_read_addr[2]);

--C1_e[0] is memory:memory|e[0] at LC_X27_Y26_N6
--operation mode is normal

C1_e[0] = DFFEAS(C1L4, GLOBAL(clock), VCC, , C1L14, B1_data_in[0], , , VCC);


--C1L53 is memory:memory|data_out[0]~43 at LC_X29_Y26_N2
--operation mode is normal

C1L53 = rst & (!B1_mem_read_addr[2] # !B1_mem_read_addr[1]);


--B1_flag.01 is cpu:cpu|flag.01 at LC_X32_Y24_N4
--operation mode is normal

B1_flag.01_lut_out = !B1_flag.00;
B1_flag.01 = DFFEAS(B1_flag.01_lut_out, GLOBAL(clock), GLOBAL(rst), , B1L551, , , , );


--C1_c[1] is memory:memory|c[1] at LC_X28_Y27_N5
--operation mode is normal

C1_c[1]_lut_out = B1_data_in[1];
C1_c[1] = DFFEAS(C1_c[1]_lut_out, GLOBAL(clock), VCC, , C1L32, , , , );


--C1_d[1] is memory:memory|d[1] at LC_X28_Y26_N3
--operation mode is normal

C1_d[1]_lut_out = B1_data_in[1];
C1_d[1] = DFFEAS(C1_d[1]_lut_out, GLOBAL(clock), VCC, , C1L92, , , , );


--C1_a[1] is memory:memory|a[1] at LC_X28_Y26_N6
--operation mode is normal

C1_a[1]_lut_out = B1_data_in[1];
C1_a[1] = DFFEAS(C1_a[1]_lut_out, GLOBAL(clock), GLOBAL(rst), , C1L2, , , , );


--C1L5 is memory:memory|Select~238 at LC_X27_Y26_N5
--operation mode is normal

C1_b[1]_qfbk = C1_b[1];
C1L5 = B1_mem_read_addr[0] & (C1_b[1]_qfbk # B1_mem_read_addr[2]) # !B1_mem_read_addr[0] & C1_a[1] & (!B1_mem_read_addr[2]);

--C1_b[1] is memory:memory|b[1] at LC_X27_Y26_N5
--operation mode is normal

C1_b[1] = DFFEAS(C1L5, GLOBAL(clock), GLOBAL(rst), , C1L1, B1_data_in[1], , , VCC);


--C1_f[1] is memory:memory|f[1] at LC_X27_Y25_N5
--operation mode is normal

C1_f[1]_lut_out = B1_data_in[1];
C1_f[1] = DFFEAS(C1_f[1]_lut_out, GLOBAL(clock), VCC, , C1L74, , , , );


--C1L6 is memory:memory|Select~239 at LC_X27_Y26_N9
--operation mode is normal

C1_e[1]_qfbk = C1_e[1];
C1L6 = C1L5 & (C1_f[1] # !B1_mem_read_addr[2]) # !C1L5 & (C1_e[1]_qfbk & B1_mem_read_addr[2]);

--C1_e[1] is memory:memory|e[1] at LC_X27_Y26_N9
--operation mode is normal

C1_e[1] = DFFEAS(C1L6, GLOBAL(clock), VCC, , C1L14, B1_data_in[1], , , VCC);


--B1L41 is cpu:cpu|Mux~130 at LC_X30_Y26_N9
--operation mode is normal

B1_r[2][1]_qfbk = B1_r[2][1];
B1L41 = D1_instruction[0] & D1_instruction[1] # !D1_instruction[0] & (D1_instruction[1] & B1_r[2][1]_qfbk # !D1_instruction[1] & (B1_r[0][1]));

--B1_r[2][1] is cpu:cpu|r[2][1] at LC_X30_Y26_N9
--operation mode is normal

B1_r[2][1] = DFFEAS(B1L41, GLOBAL(clock), VCC, , B1L921, B1L53, , , VCC);


--B1L51 is cpu:cpu|Mux~131 at LC_X30_Y26_N7
--operation mode is normal

B1L51 = D1_instruction[0] & (B1L41 & (B1_r[3][1]) # !B1L41 & B1_r[1][1]) # !D1_instruction[0] & (B1L41);


--C1_c[2] is memory:memory|c[2] at LC_X28_Y27_N9
--operation mode is normal

C1_c[2]_lut_out = B1_data_in[2];
C1_c[2] = DFFEAS(C1_c[2]_lut_out, GLOBAL(clock), VCC, , C1L32, , , , );


--C1_d[2] is memory:memory|d[2] at LC_X28_Y26_N7
--operation mode is normal

C1_d[2]_lut_out = GND;
C1_d[2] = DFFEAS(C1_d[2]_lut_out, GLOBAL(clock), VCC, , C1L92, B1_data_in[2], , , VCC);


--C1_b[2] is memory:memory|b[2] at LC_X27_Y26_N4
--operation mode is normal

C1_b[2]_lut_out = !B1_data_in[2];
C1_b[2] = DFFEAS(C1_b[2]_lut_out, GLOBAL(clock), GLOBAL(rst), , C1L1, , , , );


--C1L7 is memory:memory|Select~240 at LC_X28_Y26_N5
--operation mode is normal

C1_a[2]_qfbk = C1_a[2];
C1L7 = B1_mem_read_addr[2] & B1_mem_read_addr[0] # !B1_mem_read_addr[2] & (B1_mem_read_addr[0] & (!C1_b[2]) # !B1_mem_read_addr[0] & C1_a[2]_qfbk);

--C1_a[2] is memory:memory|a[2] at LC_X28_Y26_N5
--operation mode is normal

C1_a[2] = DFFEAS(C1L7, GLOBAL(clock), GLOBAL(rst), , C1L2, B1_data_in[2], , , VCC);


--C1_f[2] is memory:memory|f[2] at LC_X27_Y25_N4
--operation mode is normal

C1_f[2]_lut_out = B1_data_in[2];
C1_f[2] = DFFEAS(C1_f[2]_lut_out, GLOBAL(clock), VCC, , C1L74, , , , );


--C1L8 is memory:memory|Select~241 at LC_X27_Y26_N3
--operation mode is normal

C1_e[2]_qfbk = C1_e[2];
C1L8 = C1L7 & (C1_f[2] # !B1_mem_read_addr[2]) # !C1L7 & (C1_e[2]_qfbk & B1_mem_read_addr[2]);

--C1_e[2] is memory:memory|e[2] at LC_X27_Y26_N3
--operation mode is normal

C1_e[2] = DFFEAS(C1L8, GLOBAL(clock), VCC, , C1L14, B1_data_in[2], , , VCC);


--B1L61 is cpu:cpu|Mux~132 at LC_X30_Y26_N8
--operation mode is normal

B1L61 = D1_instruction[1] & (D1_instruction[0]) # !D1_instruction[1] & (D1_instruction[0] & B1_r[1][2] # !D1_instruction[0] & (B1_r[0][2]));


--B1L71 is cpu:cpu|Mux~133 at LC_X29_Y27_N0
--operation mode is normal

B1_r[3][2]_qfbk = B1_r[3][2];
B1L71 = B1L61 & (B1_r[3][2]_qfbk # !D1_instruction[1]) # !B1L61 & B1_r[2][2] & (D1_instruction[1]);

--B1_r[3][2] is cpu:cpu|r[3][2] at LC_X29_Y27_N0
--operation mode is normal

B1_r[3][2] = DFFEAS(B1L71, GLOBAL(clock), VCC, , B1L531, B1L93, , , VCC);


--L3L4 is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~26 at LC_X30_Y24_N7
--operation mode is arithmetic

L3L4 = G1_decoder_node[1][1] $ G1_decoder_node[0][2] $ L3L2;

--L3L5 is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~28 at LC_X30_Y24_N7
--operation mode is arithmetic

L3L5_cout_0 = G1_decoder_node[1][1] & !G1_decoder_node[0][2] & !L3L2 # !G1_decoder_node[1][1] & (!L3L2 # !G1_decoder_node[0][2]);
L3L5 = CARRY(L3L5_cout_0);

--L3L6 is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~28COUT1_37 at LC_X30_Y24_N7
--operation mode is arithmetic

L3L6_cout_1 = G1_decoder_node[1][1] & !G1_decoder_node[0][2] & !L3L3 # !G1_decoder_node[1][1] & (!L3L3 # !G1_decoder_node[0][2]);
L3L6 = CARRY(L3L6_cout_1);


--C1_c[3] is memory:memory|c[3] at LC_X28_Y27_N8
--operation mode is normal

C1_c[3]_lut_out = GND;
C1_c[3] = DFFEAS(C1_c[3]_lut_out, GLOBAL(clock), VCC, , C1L32, B1_data_in[3], , , VCC);


--C1_d[3] is memory:memory|d[3] at LC_X28_Y26_N4
--operation mode is normal

C1_d[3]_lut_out = GND;
C1_d[3] = DFFEAS(C1_d[3]_lut_out, GLOBAL(clock), VCC, , C1L92, B1_data_in[3], , , VCC);


--C1_a[3] is memory:memory|a[3] at LC_X28_Y26_N2
--operation mode is normal

C1_a[3]_lut_out = GND;
C1_a[3] = DFFEAS(C1_a[3]_lut_out, GLOBAL(clock), GLOBAL(rst), , C1L2, B1_data_in[3], , , VCC);


--C1L9 is memory:memory|Select~242 at LC_X27_Y26_N7
--operation mode is normal

C1_e[3]_qfbk = C1_e[3];
C1L9 = B1_mem_read_addr[0] & (B1_mem_read_addr[2]) # !B1_mem_read_addr[0] & (B1_mem_read_addr[2] & (C1_e[3]_qfbk) # !B1_mem_read_addr[2] & C1_a[3]);

--C1_e[3] is memory:memory|e[3] at LC_X27_Y26_N7
--operation mode is normal

C1_e[3] = DFFEAS(C1L9, GLOBAL(clock), VCC, , C1L14, B1_data_in[3], , , VCC);


--C1_f[3] is memory:memory|f[3] at LC_X27_Y25_N6
--operation mode is normal

C1_f[3]_lut_out = B1_data_in[3];
C1_f[3] = DFFEAS(C1_f[3]_lut_out, GLOBAL(clock), VCC, , C1L74, , , , );


--C1L01 is memory:memory|Select~243 at LC_X27_Y26_N8
--operation mode is normal

C1_b[3]_qfbk = C1_b[3];
C1L01 = B1_mem_read_addr[0] & (C1L9 & (C1_f[3]) # !C1L9 & C1_b[3]_qfbk) # !B1_mem_read_addr[0] & C1L9;

--C1_b[3] is memory:memory|b[3] at LC_X27_Y26_N8
--operation mode is normal

C1_b[3] = DFFEAS(C1L01, GLOBAL(clock), GLOBAL(rst), , C1L1, B1_data_in[3], , , VCC);


--L3L7 is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~31 at LC_X30_Y24_N8
--operation mode is normal

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