L3L7 = G1_decoder_node[0][3] $ (L3L5 $ !G1_decoder_node[1][2]);


--L6L1 is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~7 at LC_X30_Y25_N9
--operation mode is normal

L6L1 = G1_decoder_node[3][0] $ (G1_decoder_node[2][1]);


--B1L81 is cpu:cpu|Mux~134 at LC_X30_Y26_N5
--operation mode is normal

B1L81 = D1_instruction[0] & D1_instruction[1] # !D1_instruction[0] & (D1_instruction[1] & B1_r[2][3] # !D1_instruction[1] & (B1_r[0][3]));


--B1L91 is cpu:cpu|Mux~135 at LC_X30_Y26_N2
--operation mode is normal

B1L91 = B1L81 & (B1_r[3][3] # !D1_instruction[0]) # !B1L81 & B1_r[1][3] & D1_instruction[0];


--B1L441 is cpu:cpu|ram_addr[0]~195 at LC_X29_Y25_N5
--operation mode is normal

B1L441 = !B1L141 & !D1_instruction[10] & !B1L041 # !D1_instruction[11];


--C1L32 is memory:memory|c[0]~3 at LC_X28_Y25_N1
--operation mode is normal

B1_mem_write_addr[1]_qfbk = B1_mem_write_addr[1];
C1L32 = !B1_mem_write_addr[2] & rst & B1_mem_write_addr[1]_qfbk & !B1_mem_write_addr[0];

--B1_mem_write_addr[1] is cpu:cpu|mem_write_addr[1] at LC_X28_Y25_N1
--operation mode is normal

B1_mem_write_addr[1] = DFFEAS(C1L32, GLOBAL(clock), VCC, , B1L501, D1_instruction[1], , , VCC);


--C1L92 is memory:memory|d[0]~3 at LC_X28_Y25_N2
--operation mode is normal

C1L92 = !B1_mem_write_addr[2] & B1_mem_write_addr[1] & rst & B1_mem_write_addr[0];


--C1L14 is memory:memory|e[0]~3 at LC_X28_Y25_N8
--operation mode is normal

B1_mem_write_addr[2]_qfbk = B1_mem_write_addr[2];
C1L14 = rst & !B1_mem_write_addr[1] & B1_mem_write_addr[2]_qfbk & !B1_mem_write_addr[0];

--B1_mem_write_addr[2] is cpu:cpu|mem_write_addr[2] at LC_X28_Y25_N8
--operation mode is normal

B1_mem_write_addr[2] = DFFEAS(C1L14, GLOBAL(clock), VCC, , B1L501, D1_instruction[2], , , VCC);


--B1_flag.00 is cpu:cpu|flag.00 at LC_X32_Y24_N2
--operation mode is normal

B1_flag.00_lut_out = !B1_flag.10;
B1_flag.00 = DFFEAS(B1_flag.00_lut_out, GLOBAL(clock), GLOBAL(rst), , B1L551, , , , );


--B1L001 is cpu:cpu|mem_read_addr[0]~7 at LC_X28_Y25_N3
--operation mode is normal

B1L001 = !D1_instruction[8] & !B1_flag.00 & rst & B1L551;


--C1L1 is memory:memory|Decoder~113 at LC_X28_Y25_N4
--operation mode is normal

B1_mem_write_addr[0]_qfbk = B1_mem_write_addr[0];
C1L1 = !B1_mem_write_addr[1] & B1_mem_write_addr[0]_qfbk & !B1_mem_write_addr[2];

--B1_mem_write_addr[0] is cpu:cpu|mem_write_addr[0] at LC_X28_Y25_N4
--operation mode is normal

B1_mem_write_addr[0] = DFFEAS(C1L1, GLOBAL(clock), VCC, , B1L501, D1_instruction[0], , , VCC);


--C1L2 is memory:memory|Decoder~114 at LC_X28_Y25_N6
--operation mode is normal

C1L2 = !B1_mem_write_addr[2] & (!B1_mem_write_addr[1] & !B1_mem_write_addr[0]);


--C1L74 is memory:memory|f[0]~3 at LC_X28_Y25_N7
--operation mode is normal

C1L74 = B1_mem_write_addr[2] & !B1_mem_write_addr[1] & rst & B1_mem_write_addr[0];


--B1_data_in[1] is cpu:cpu|data_in[1] at LC_X29_Y25_N2
--operation mode is normal

B1_data_in[1]_lut_out = GND;
B1_data_in[1] = DFFEAS(B1_data_in[1]_lut_out, GLOBAL(clock), VCC, , B1L19, B1L7, , , VCC);


--G1_decoder_node[0][1] is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|decoder_node[0][1] at LC_X31_Y27_N7
--operation mode is normal

G1_decoder_node[0][1] = LCELL(B1L7 & B1L31);


--G1_decoder_node[1][0] is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|decoder_node[1][0] at LC_X30_Y26_N6
--operation mode is normal

G1_decoder_node[1][0] = LCELL(B1L51 & (B1L9));


--B1_data_in[2] is cpu:cpu|data_in[2] at LC_X28_Y27_N2
--operation mode is normal

B1_data_in[2]_lut_out = B1L11;
B1_data_in[2] = DFFEAS(B1_data_in[2]_lut_out, GLOBAL(clock), VCC, , B1L19, , , , );


--G1_decoder_node[2][0] is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|decoder_node[2][0] at LC_X29_Y27_N8
--operation mode is normal

G1_decoder_node[2][0] = LCELL(B1L9 & (B1L71));


--G1_decoder_node[3][0] is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|decoder_node[3][0] at LC_X30_Y25_N0
--operation mode is normal

G1_decoder_node[3][0] = LCELL(B1L9 & B1L91);


--G1_decoder_node[2][1] is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|decoder_node[2][1] at LC_X29_Y27_N7
--operation mode is normal

G1_decoder_node[2][1] = LCELL(B1L7 & (B1L71));


--B1L19 is cpu:cpu|data_in[0]~29 at LC_X29_Y25_N7
--operation mode is normal

B1L19 = rst & B1L551 & D1_instruction[8] & B1_flag.10;


--B1L501 is cpu:cpu|mem_write_addr[0]~37 at LC_X28_Y25_N9
--operation mode is normal

B1L501 = D1_instruction[8] & !B1_flag.00 & rst & B1L551;


--G1_decoder_node[0][2] is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|decoder_node[0][2] at LC_X31_Y27_N8
--operation mode is normal

G1_decoder_node[0][2] = LCELL(B1L31 & (B1L11));


--G1_decoder_node[1][1] is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|decoder_node[1][1] at LC_X30_Y26_N3
--operation mode is normal

G1_decoder_node[1][1] = LCELL(B1L51 & (B1L7));


--G1_decoder_node[0][3] is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|decoder_node[0][3] at LC_X31_Y25_N3
--operation mode is normal

G1_decoder_node[0][3] = LCELL(B1L5 & (B1L31));


--G1_decoder_node[1][2] is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|decoder_node[1][2] at LC_X30_Y26_N4
--operation mode is normal

G1_decoder_node[1][2] = LCELL(B1L51 & (B1L11));


--B1L211 is cpu:cpu|r[0][1]~1520 at LC_X29_Y27_N1
--operation mode is normal

B1L211 = !D1_instruction[4] & rst & !D1_instruction[5] & B1L821;


--B1L56 is cpu:cpu|Select~10959 at LC_X31_Y24_N8
--operation mode is normal

B1L56 = B1_r[0][3] & B1L04 & (D1_instruction[5] # D1_instruction[4]);


--B1L221 is cpu:cpu|r[1][1]~1521 at LC_X29_Y27_N4
--operation mode is normal

B1L221 = D1_instruction[4] & rst & !D1_instruction[5] & B1L821;


--B1L66 is cpu:cpu|Select~10960 at LC_X29_Y25_N3
--operation mode is normal

B1L66 = B1L04 & B1_r[1][3] & (D1_instruction[5] # !D1_instruction[4]);


--B1L921 is cpu:cpu|r[2][1]~1522 at LC_X29_Y27_N2
--operation mode is normal

B1L921 = !D1_instruction[4] & rst & D1_instruction[5] & B1L821;


--B1L76 is cpu:cpu|Select~10961 at LC_X29_Y24_N5
--operation mode is normal

B1L76 = B1L04 & B1_r[2][3] & (D1_instruction[4] # !D1_instruction[5]);


--B1L531 is cpu:cpu|r[3][1]~1523 at LC_X29_Y27_N3
--operation mode is normal

B1L531 = D1_instruction[4] & rst & D1_instruction[5] & B1L821;


--B1L86 is cpu:cpu|Select~10962 at LC_X31_Y24_N2
--operation mode is normal

B1L86 = B1L04 & B1_r[3][3] & (!D1_instruction[5] # !D1_instruction[4]);


--clock is clock at PIN_L2
--operation mode is input

clock = INPUT();


--rst is rst at PIN_L3
--operation mode is input

rst = INPUT();


--r0[0] is r0[0] at PIN_L7
--operation mode is output

r0[0] = OUTPUT(B1_r[0][0]);


--r0[1] is r0[1] at PIN_D9
--operation mode is output

r0[1] = OUTPUT(B1_r[0][1]);


--r0[2] is r0[2] at PIN_A12
--operation mode is output

r0[2] = OUTPUT(B1_r[0][2]);


--r0[3] is r0[3] at PIN_B12
--operation mode is output

r0[3] = OUTPUT(B1_r[0][3]);


--r1[0] is r1[0] at PIN_B8
--operation mode is output

r1[0] = OUTPUT(B1_r[1][0]);


--r1[1] is r1[1] at PIN_E8
--operation mode is output

r1[1] = OUTPUT(B1_r[1][1]);


--r1[2] is r1[2] at PIN_C14
--operation mode is output

r1[2] = OUTPUT(B1_r[1][2]);


--r1[3] is r1[3] at PIN_C12
--operation mode is output

r1[3] = OUTPUT(B1_r[1][3]);


--r2[0] is r2[0] at PIN_G9
--operation mode is output

r2[0] = OUTPUT(B1_r[2][0]);


--r2[1] is r2[1] at PIN_E9
--operation mode is output

r2[1] = OUTPUT(B1_r[2][1]);


--r2[2] is r2[2] at PIN_K15
--operation mode is output

r2[2] = OUTPUT(B1_r[2][2]);


--r2[3] is r2[3] at PIN_B13
--operation mode is output

r2[3] = OUTPUT(B1_r[2][3]);


--r3[0] is r3[0] at PIN_F9
--operation mode is output

r3[0] = OUTPUT(B1_r[3][0]);


--r3[1] is r3[1] at PIN_N10
--operation mode is output

r3[1] = OUTPUT(B1_r[3][1]);


--r3[2] is r3[2] at PIN_D8
--operation mode is output

r3[2] = OUTPUT(B1_r[3][2]);


--r3[3] is r3[3] at PIN_D12
--operation mode is output

r3[3] = OUTPUT(B1_r[3][3]);


--instruction[0] is instruction[0] at PIN_C9
--operation mode is output

instruction[0] = OUTPUT(D1_instruction[0]);


--instruction[1] is instruction[1] at PIN_C13
--operation mode is output

instruction[1] = OUTPUT(D1_instruction[1]);


--instruction[2] is instruction[2] at PIN_D13
--operation mode is output

instruction[2] = OUTPUT(D1_instruction[2]);


--instruction[3] is instruction[3] at PIN_W18
--operation mode is output

instruction[3] = OUTPUT(A1L73);


--instruction[4] is instruction[4] at PIN_K8
--operation mode is output

instruction[4] = OUTPUT(D1_instruction[4]);


--instruction[5] is instruction[5] at PIN_H10
--operation mode is output

instruction[5] = OUTPUT(D1_instruction[5]);


--instruction[6] is instruction[6] at PIN_AB19
--operation mode is output

instruction[6] = OUTPUT(A1L73);


--instruction[7] is instruction[7] at PIN_AA17
--operation mode is output

instruction[7] = OUTPUT(A1L73);


--instruction[8] is instruction[8] at PIN_J8
--operation mode is output

instruction[8] = OUTPUT(D1_instruction[8]);


--instruction[9] is instruction[9] at PIN_J9
--operation mode is output

instruction[9] = OUTPUT(D1_instruction[9]);


--instruction[10] is instruction[10] at PIN_F10
--operation mode is output

instruction[10] = OUTPUT(D1_instruction[10]);


--instruction[11] is instruction[11] at PIN_K10
--operation mode is output

instruction[11] = OUTPUT(D1_instruction[11]);


--A1L73 is ~STRATIX_FITTER_CREATED_GND~I at LC_X3_Y1_N2
--operation mode is normal

A1L73 = GND;