module cpu(ram_addr,mem_read_addr,mem_write_addr,data_out,instruction,data_in,clock,rst,r0,r1,r2,r3);

output [4:0]ram_addr;
output [3:0]mem_read_addr,mem_write_addr,data_in;
input [11:0]instruction;
input [3:0]data_out;
input clock,rst;

reg [3:0]mem_read_addr,mem_write_addr,data_in;
reg [4:0]ram_addr;
reg [3:0] r[0:3];
reg [1:0] flag;

output	[3:0]r0,r1,r2,r3;
assign r0 = r[0];
assign r1 = r[1];
assign r2 = r[2];
assign r3 = r[3];




always@(posedge clock or negedge rst)
begin
if(rst==0)
begin
    ram_addr=0;
    flag=0;
end
else
begin
	case(instruction[11:8])
	4'd0:           ram_addr=ram_addr+1;
	4'd1:	begin
			r[instruction[5:4]]=r[instruction[5:4]]+r[instruction[1:0]];
			ram_addr=ram_addr+1;
		end
	4'd2:	begin
			r[instruction[5:4]]=r[instruction[5:4]]-r[instruction[1:0]];
			ram_addr=ram_addr+1;
		end
	4'd3:	begin
			r[instruction[5:4]]=r[instruction[5:4]]*r[instruction[1:0]];
			ram_addr=ram_addr+1;
		end	
	4'd4:	begin
			r[instruction[5:4]]=r[instruction[5:4]]<<1;
			ram_addr=ram_addr+1;
		end
	4'd5:	begin
			r[instruction[5:4]]=r[instruction[5:4]]>>1;
			ram_addr=ram_addr+1;
		end
	4'd6:	begin
			r[instruction[5:4]]={r[instruction[5:4]][2:0],r[instruction[5:4]][3]};
			ram_addr=ram_addr+1;
		end		
	4'd7:	begin
			r[instruction[5:4]]={r[instruction[5:4]][0],r[instruction[5:4]][3:1]};
			ram_addr=ram_addr+1;
		end				
	4'd8:	begin
		case(flag)
               			2'b00:
               				begin
               					mem_read_addr=instruction[3:0];
               					flag=2'b01;
                    				end
               
               			2'b01:
               				flag=2'b10;
						2'b10:
							begin
               					r[instruction[5:4]]=data_out;
	               				ram_addr=ram_addr+1;
              				 	flag=2'b00;
                 			     	end
                endcase
		end
	4'd9:	begin
		case(flag)
   		       2'b00:
   		       	        begin
               					mem_write_addr=instruction[3:0];
               					flag=2'b01;end
           			2'b01:flag=2'b10;
					2'b10:
           				begin
           
               					data_in=r[instruction[5:4]];
           					ram_addr=ram_addr+1;
           					flag=2'b00;
           				end
           		endcase
		end
	4'd10:	begin
			
			r[instruction[5:4]]=instruction[3:0];
			ram_addr=ram_addr+1;
		end		
	endcase
end
end
endmodule