module prog_ram(instruction,ram_addr);
input [4:0] ram_addr;    
output [11:0] instruction;
reg [11:0] instruction;

always@(ram_addr)
    case(ram_addr[4:0])   
     5'd0:instruction=12'b000000000000;    //NOP
     5'd1:instruction=12'b100000000000; //Load R0,Y mem0000
     5'd2:instruction=12'b100000010001; //Load R1,X mem0001
     5'd3:instruction=12'b000100010000; //ADD R1,R0
     5'd4:instruction=12'b010100010000; //SR   R1
     5'd5:instruction=12'b100100010010; //STORE mem0010,R1
     5'd6:instruction=12'b001000010000; //SUB R1,R0
     5'd7:instruction=12'b010000010000; //SL  R1
     5'd8:instruction=12'b100100010011; //STORE mem0011,R1
     5'd9:instruction=12'b001100010000; //MUL R1,R0
     5'd10:instruction=12'b011100010000; //RR  R1
     5'd11:instruction=12'b100100010100; //STORE mem0100,R1
     5'd12:instruction=12'b000100010000; //ADD R1,R0
     5'd13:instruction=12'b011000010000; //RL   R1
     5'd14:instruction=12'b100100010101; //STORE mem0101,R1
     5'd15:instruction=12'b100000000010; //LOAD R0,mem0010
     5'd16:instruction=12'b100000010011; //LOAD R1,mem0011
     5'd17:instruction=12'b100000100100; //LOAD R2,mem0100
     5'd18:instruction=12'b100000110101; //LOAD R3,mem0101
    endcase
    
endmodule