|lab2_sim
clock => clock~0.IN2
rst => rst~0.IN2
r0[0] <= cpu:cpu.port8
r0[1] <= cpu:cpu.port8
r0[2] <= cpu:cpu.port8
r0[3] <= cpu:cpu.port8
r1[0] <= cpu:cpu.port9
r1[1] <= cpu:cpu.port9
r1[2] <= cpu:cpu.port9
r1[3] <= cpu:cpu.port9
r2[0] <= cpu:cpu.port10
r2[1] <= cpu:cpu.port10
r2[2] <= cpu:cpu.port10
r2[3] <= cpu:cpu.port10
r3[0] <= cpu:cpu.port11
r3[1] <= cpu:cpu.port11
r3[2] <= cpu:cpu.port11
r3[3] <= cpu:cpu.port11
instruction[0] <= instruction[0]~11.DB_MAX_OUTPUT_PORT_TYPE
instruction[1] <= instruction[1]~10.DB_MAX_OUTPUT_PORT_TYPE
instruction[2] <= instruction[2]~9.DB_MAX_OUTPUT_PORT_TYPE
instruction[3] <= instruction[3]~8.DB_MAX_OUTPUT_PORT_TYPE
instruction[4] <= instruction[4]~7.DB_MAX_OUTPUT_PORT_TYPE
instruction[5] <= instruction[5]~6.DB_MAX_OUTPUT_PORT_TYPE
instruction[6] <= instruction[6]~5.DB_MAX_OUTPUT_PORT_TYPE
instruction[7] <= instruction[7]~4.DB_MAX_OUTPUT_PORT_TYPE
instruction[8] <= instruction[8]~3.DB_MAX_OUTPUT_PORT_TYPE
instruction[9] <= instruction[9]~2.DB_MAX_OUTPUT_PORT_TYPE
instruction[10] <= instruction[10]~1.DB_MAX_OUTPUT_PORT_TYPE
instruction[11] <= instruction[11]~0.DB_MAX_OUTPUT_PORT_TYPE


|lab2_sim|cpu:cpu
ram_addr[0] <= ram_addr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ram_addr[1] <= ram_addr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ram_addr[2] <= ram_addr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ram_addr[3] <= ram_addr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ram_addr[4] <= ram_addr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mem_read_addr[0] <= mem_read_addr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mem_read_addr[1] <= mem_read_addr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mem_read_addr[2] <= mem_read_addr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mem_read_addr[3] <= mem_read_addr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mem_write_addr[0] <= mem_write_addr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mem_write_addr[1] <= mem_write_addr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mem_write_addr[2] <= mem_write_addr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mem_write_addr[3] <= mem_write_addr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[0] => always0~91.DATAB
data_out[0] => always0~95.DATAB
data_out[0] => always0~99.DATAB
data_out[0] => always0~103.DATAB
data_out[1] => always0~90.DATAB
data_out[1] => always0~94.DATAB
data_out[1] => always0~98.DATAB
data_out[1] => always0~102.DATAB
data_out[2] => always0~89.DATAB
data_out[2] => always0~93.DATAB
data_out[2] => always0~97.DATAB
data_out[2] => always0~101.DATAB
data_out[3] => always0~88.DATAB
data_out[3] => always0~92.DATAB
data_out[3] => always0~96.DATAB
data_out[3] => always0~100.DATAB
instruction[0] => Mux~0.IN1
instruction[0] => Mux~1.IN1
instruction[0] => Mux~2.IN1
instruction[0] => Mux~3.IN1
instruction[0] => always0~107.DATAB
instruction[0] => always0~111.DATAB
instruction[0] => always0~115.DATAB
instruction[0] => always0~119.DATAB
instruction[0] => mem_read_addr[0]~reg0.DATAIN
instruction[0] => mem_write_addr[0]~reg0.DATAIN
instruction[1] => Mux~0.IN0
instruction[1] => Mux~1.IN0
instruction[1] => Mux~2.IN0
instruction[1] => Mux~3.IN0
instruction[1] => always0~106.DATAB
instruction[1] => always0~110.DATAB
instruction[1] => always0~114.DATAB
instruction[1] => always0~118.DATAB
instruction[1] => mem_read_addr[1]~reg0.DATAIN
instruction[1] => mem_write_addr[1]~reg0.DATAIN
instruction[2] => always0~105.DATAB
instruction[2] => always0~109.DATAB
instruction[2] => always0~113.DATAB
instruction[2] => always0~117.DATAB
instruction[2] => mem_read_addr[2]~reg0.DATAIN
instruction[2] => mem_write_addr[2]~reg0.DATAIN
instruction[3] => always0~104.DATAB
instruction[3] => always0~108.DATAB
instruction[3] => always0~112.DATAB
instruction[3] => always0~116.DATAB
instruction[3] => mem_read_addr[3]~reg0.DATAIN
instruction[3] => mem_write_addr[3]~reg0.DATAIN
instruction[4] => Mux~4.IN1
instruction[4] => Mux~5.IN1
instruction[4] => Mux~6.IN1
instruction[4] => Mux~7.IN1
instruction[4] => Decoder~0.IN1
instruction[5] => Mux~4.IN0
instruction[5] => Mux~5.IN0
instruction[5] => Mux~6.IN0
instruction[5] => Mux~7.IN0
instruction[5] => Decoder~0.IN0
instruction[6] => ~NO_FANOUT~
instruction[7] => ~NO_FANOUT~
instruction[8] => Decoder~1.IN3
instruction[9] => Decoder~1.IN2
instruction[10] => Decoder~1.IN1
instruction[11] => Decoder~1.IN0
data_in[0] <= data_in[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_in[1] <= data_in[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_in[2] <= data_in[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_in[3] <= data_in[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
clock => ram_addr[3]~reg0.CLK
clock => ram_addr[2]~reg0.CLK
clock => ram_addr[1]~reg0.CLK
clock => ram_addr[0]~reg0.CLK
clock => r[3][3].CLK
clock => r[3][2].CLK
clock => r[3][1].CLK
clock => r[3][0].CLK
clock => r[2][3].CLK
clock => r[2][2].CLK
clock => r[2][1].CLK
clock => r[2][0].CLK
clock => r[1][3].CLK
clock => r[1][2].CLK
clock => r[1][1].CLK
clock => r[1][0].CLK
clock => r[0][3].CLK
clock => r[0][2].CLK
clock => r[0][1].CLK
clock => r[0][0].CLK
clock => mem_read_addr[3]~reg0.CLK
clock => mem_read_addr[2]~reg0.CLK
clock => mem_read_addr[1]~reg0.CLK
clock => mem_read_addr[0]~reg0.CLK
clock => mem_write_addr[3]~reg0.CLK
clock => mem_write_addr[2]~reg0.CLK
clock => mem_write_addr[1]~reg0.CLK
clock => mem_write_addr[0]~reg0.CLK
clock => data_in[3]~reg0.CLK
clock => data_in[2]~reg0.CLK
clock => data_in[1]~reg0.CLK
clock => data_in[0]~reg0.CLK
clock => ram_addr[4]~reg0.CLK
clock => flag~0.IN1
rst => ram_addr[3]~reg0.ACLR
rst => ram_addr[2]~reg0.ACLR
rst => ram_addr[1]~reg0.ACLR
rst => ram_addr[0]~reg0.ACLR
rst => ram_addr[4]~reg0.ACLR
rst => r[3][3].ENA
rst => r[3][2].ENA
rst => r[3][1].ENA
rst => r[3][0].ENA
rst => r[2][3].ENA
rst => r[2][2].ENA
rst => r[2][1].ENA
rst => r[2][0].ENA
rst => r[1][3].ENA
rst => r[1][2].ENA
rst => r[1][1].ENA
rst => r[1][0].ENA
rst => r[0][3].ENA
rst => r[0][2].ENA
rst => r[0][1].ENA
rst => r[0][0].ENA
rst => flag~1.IN1
r0[0] <= r[0][0].DB_MAX_OUTPUT_PORT_TYPE
r0[1] <= r[0][1].DB_MAX_OUTPUT_PORT_TYPE
r0[2] <= r[0][2].DB_MAX_OUTPUT_PORT_TYPE
r0[3] <= r[0][3].DB_MAX_OUTPUT_PORT_TYPE
r1[0] <= r[1][0].DB_MAX_OUTPUT_PORT_TYPE
r1[1] <= r[1][1].DB_MAX_OUTPUT_PORT_TYPE
r1[2] <= r[1][2].DB_MAX_OUTPUT_PORT_TYPE
r1[3] <= r[1][3].DB_MAX_OUTPUT_PORT_TYPE
r2[0] <= r[2][0].DB_MAX_OUTPUT_PORT_TYPE
r2[1] <= r[2][1].DB_MAX_OUTPUT_PORT_TYPE
r2[2] <= r[2][2].DB_MAX_OUTPUT_PORT_TYPE
r2[3] <= r[2][3].DB_MAX_OUTPUT_PORT_TYPE
r3[0] <= r[3][0].DB_MAX_OUTPUT_PORT_TYPE
r3[1] <= r[3][1].DB_MAX_OUTPUT_PORT_TYPE
r3[2] <= r[3][2].DB_MAX_OUTPUT_PORT_TYPE
r3[3] <= r[3][3].DB_MAX_OUTPUT_PORT_TYPE


|lab2_sim|memory:memory
data_in[0] => a[0].DATAIN
data_in[0] => b[0].DATAIN
data_in[0] => c[0].DATAIN
data_in[0] => d[0].DATAIN
data_in[0] => e[0].DATAIN
data_in[0] => f[0].DATAIN
data_in[1] => a[1].DATAIN
data_in[1] => b[1].DATAIN
data_in[1] => c[1].DATAIN
data_in[1] => d[1].DATAIN
data_in[1] => e[1].DATAIN
data_in[1] => f[1].DATAIN
data_in[2] => a[2].DATAIN
data_in[2] => c[2].DATAIN
data_in[2] => d[2].DATAIN
data_in[2] => e[2].DATAIN
data_in[2] => f[2].DATAIN
data_in[2] => b[2].DATAIN
data_in[3] => b[3].DATAIN
data_in[3] => c[3].DATAIN
data_in[3] => d[3].DATAIN
data_in[3] => e[3].DATAIN
data_in[3] => f[3].DATAIN
data_in[3] => a[3].DATAIN
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mem_write_addr[0] => Decoder~1.IN3
mem_write_addr[1] => Decoder~1.IN2
mem_write_addr[2] => Decoder~1.IN1
mem_write_addr[3] => Decoder~1.IN0
mem_read_addr[0] => Decoder~0.IN3
mem_read_addr[1] => Decoder~0.IN2
mem_read_addr[2] => Decoder~0.IN1
mem_read_addr[3] => Decoder~0.IN0
clock => a[2].CLK
clock => a[1].CLK
clock => a[0].CLK
clock => b[3].CLK
clock => b[2].CLK
clock => b[1].CLK
clock => b[0].CLK
clock => data_out[3]~reg0.CLK
clock => data_out[2]~reg0.CLK
clock => data_out[1]~reg0.CLK
clock => data_out[0]~reg0.CLK
clock => c[3].CLK
clock => c[2].CLK
clock => c[1].CLK
clock => c[0].CLK
clock => d[3].CLK
clock => d[2].CLK
clock => d[1].CLK
clock => d[0].CLK
clock => e[3].CLK
clock => e[2].CLK
clock => e[1].CLK
clock => e[0].CLK
clock => f[3].CLK
clock => f[2].CLK
clock => f[1].CLK
clock => f[0].CLK
clock => a[3].CLK
rst => a[2].ACLR
rst => a[1].ACLR
rst => a[0].ACLR
rst => b[3].ACLR
rst => b[2].PRESET
rst => b[1].ACLR
rst => b[0].ACLR
rst => a[3].ACLR
rst => data_out[3]~reg0.ENA
rst => data_out[2]~reg0.ENA
rst => data_out[1]~reg0.ENA
rst => data_out[0]~reg0.ENA


|lab2_sim|prog_ram:prog_ram
instruction[0] <= instruction[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
instruction[1] <= instruction[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
instruction[2] <= instruction[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
instruction[3] <= <GND>
instruction[4] <= instruction[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
instruction[5] <= instruction[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
instruction[6] <= <GND>
instruction[7] <= <GND>
instruction[8] <= instruction[8]$latch.DB_MAX_OUTPUT_PORT_TYPE
instruction[9] <= instruction[9]$latch.DB_MAX_OUTPUT_PORT_TYPE
instruction[10] <= instruction[10]$latch.DB_MAX_OUTPUT_PORT_TYPE
instruction[11] <= instruction[11]$latch.DB_MAX_OUTPUT_PORT_TYPE
ram_addr[0] => Decoder~0.IN4
ram_addr[1] => Decoder~0.IN3
ram_addr[2] => Decoder~0.IN2
ram_addr[3] => Decoder~0.IN1
ram_addr[4] => Decoder~0.IN0