----  Copyright (c) 2003 Launchbird Design Systems, Inc.--  All rights reserved.--  --  Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:--    Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.--    Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.--  --  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,--  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.--  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,--  OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;--  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT--  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.--  --  --  Overview:--  --    Performs a radix 2 Fast Fourier Transform.--    The FFT architecture is pipelined on a rank basis; each rank has its own butterfly and ranks are--    isolated from each other using memory interleavers.  This FFT can perform calcualations on continuous--    streaming data (one data set right after another).  More over, inputs and outputs are passed in pairs,--    doubling the bandwidth.  For instance, a 2048 point FFT can perform a transform every 1024 cycles.--  --  Interface:--  --    Synchronization:--      clock_c  : Clock input.--      enable_i : Synchronous enable.--      reset_i  : Synchronous reset.--  --    Inputs:--      sync_i     : Input sync pulse must occur one frame prior to data input.--      data_0_i   : Input data 0.  Width is 2 * precision.  Real on the left, imag on the right.--      data_1_i   : Input data 1.  Width is 2 * precision.  Real on the left, imag on the right.--  --    Outputs:--      sync_o     : Output sync pulse occurs one frame before data output.--      data_0_o   : Output data 0.  Width is 2 * precision.  Real on the left, imag on the right.--      data_1_o   : Output data 1.  Width is 2 * precision.  Real on the left, imag on the right.--  --  Built In Parameters:--  --    FFT Points   = 1024--    Precision    = 8--  --  --  --  --  Generated by Confluence 0.6.3  --  Launchbird Design Systems, Inc.  --  www.launchbird.com--  --  Build Date : Fri Aug 22 08:42:00 CDT 2003--  --  Interface--  --    Build Name    : cf_fft_1024_8--    Clock Domains : clock_c  --    Vector Input  : enable_i(1)--    Vector Input  : reset_i(1)--    Vector Input  : sync_i(1)--    Vector Input  : data_0_i(16)--    Vector Input  : data_1_i(16)--    Vector Output : sync_o(1)--    Vector Output : data_0_o(16)--    Vector Output : data_1_o(16)--  --  --  library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity cf_fft_1024_8_39 isport (clock_c : in std_logic;i1 : in  unsigned(15 downto 0);i2 : in  unsigned(15 downto 0);i3 : in  unsigned(0 downto 0);i4 : in  unsigned(0 downto 0);i5 : in  unsigned(0 downto 0);o1 : out unsigned(15 downto 0);o2 : out unsigned(15 downto 0));end entity cf_fft_1024_8_39;architecture rtl of cf_fft_1024_8_39 issignal n1 : unsigned(15 downto 0) := "0000000000000000";signal n2 : unsigned(7 downto 0);signal n3 : unsigned(7 downto 0);signal n4 : unsigned(15 downto 0) := "0000000000000000";signal n5 : unsigned(7 downto 0);signal n6 : unsigned(7 downto 0);signal n7 : unsigned(7 downto 0) := "00000000";signal n8 : unsigned(7 downto 0) := "00000000";signal n9 : unsigned(7 downto 0) := "00000000";signal n10 : unsigned(7 downto 0) := "00000000";signal n11 : unsigned(15 downto 0) := "0000000000000000";signal n12 : unsigned(7 downto 0);signal n13 : unsigned(7 downto 0);signal n14 : unsigned(15 downto 0);signal n15 : unsigned(7 downto 0);signal n16 : unsigned(7 downto 0) := "00000000";signal n17 : unsigned(15 downto 0);signal n18 : unsigned(7 downto 0);signal n19 : unsigned(7 downto 0) := "00000000";signal n20 : unsigned(7 downto 0);signal n21 : unsigned(7 downto 0) := "00000000";signal n22 : unsigned(15 downto 0);signal n23 : unsigned(7 downto 0);signal n24 : unsigned(7 downto 0) := "00000000";signal n25 : unsigned(15 downto 0);signal n26 : unsigned(7 downto 0);signal n27 : unsigned(7 downto 0) := "00000000";signal n28 : unsigned(7 downto 0);signal n29 : unsigned(7 downto 0) := "00000000";signal n30 : unsigned(7 downto 0);signal n31 : unsigned(7 downto 0);signal n32 : unsigned(15 downto 0);signal n33 : unsigned(15 downto 0) := "0000000000000000";signal n34 : unsigned(7 downto 0);signal n35 : unsigned(7 downto 0);signal n36 : unsigned(15 downto 0);signal n37 : unsigned(15 downto 0) := "0000000000000000";beginprocess (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n1 <= "0000000000000000";    elsif i4 = "1" then      n1 <= i1;    end if;  end if;end process;n2 <= n1(15 downto 15) &  n1(14 downto 14) &  n1(13 downto 13) &  n1(12 downto 12) &  n1(11 downto 11) &  n1(10 downto 10) &  n1(9 downto 9) &  n1(8 downto 8);n3 <= n1(7 downto 7) &  n1(6 downto 6) &  n1(5 downto 5) &  n1(4 downto 4) &  n1(3 downto 3) &  n1(2 downto 2) &  n1(1 downto 1) &  n1(0 downto 0);process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n4 <= "0000000000000000";    elsif i4 = "1" then      n4 <= i2;    end if;  end if;end process;n5 <= n4(15 downto 15) &  n4(14 downto 14) &  n4(13 downto 13) &  n4(12 downto 12) &  n4(11 downto 11) &  n4(10 downto 10) &  n4(9 downto 9) &  n4(8 downto 8);n6 <= n4(7 downto 7) &  n4(6 downto 6) &  n4(5 downto 5) &  n4(4 downto 4) &  n4(3 downto 3) &  n4(2 downto 2) &  n4(1 downto 1) &  n4(0 downto 0);process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n7 <= "00000000";    elsif i4 = "1" then      n7 <= n2;    end if;  end if;end process;process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n8 <= "00000000";    elsif i4 = "1" then      n8 <= n7;    end if;  end if;end process;process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n9 <= "00000000";    elsif i4 = "1" then      n9 <= n3;    end if;  end if;end process;process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n10 <= "00000000";    elsif i4 = "1" then      n10 <= n9;    end if;  end if;end process;process (clock_c) begin  if rising_edge(clock_c) then     if i4 = "1" then      case i3 is        when "0" => n11 <= "0111111100000000";        when "1" => n11 <= "0000000010000000";        when others => n11 <= "XXXXXXXXXXXXXXXX";      end case;    end if;  end if;end process;n12 <= n11(15 downto 15) &  n11(14 downto 14) &  n11(13 downto 13) &  n11(12 downto 12) &  n11(11 downto 11) &  n11(10 downto 10) &  n11(9 downto 9) &  n11(8 downto 8);n13 <= n11(7 downto 7) &  n11(6 downto 6) &  n11(5 downto 5) &  n11(4 downto 4) &  n11(3 downto 3) &  n11(2 downto 2) &  n11(1 downto 1) &  n11(0 downto 0);n14 <= unsigned(signed(n5) * signed(n12));n15 <= n14(14 downto 14) &  n14(13 downto 13) &  n14(12 downto 12) &  n14(11 downto 11) &  n14(10 downto 10) &  n14(9 downto 9) &  n14(8 downto 8) &  n14(7 downto 7);process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n16 <= "00000000";    elsif i4 = "1" then      n16 <= n15;    end if;  end if;end process;n17 <= unsigned(signed(n6) * signed(n13));n18 <= n17(14 downto 14) &  n17(13 downto 13) &  n17(12 downto 12) &  n17(11 downto 11) &  n17(10 downto 10) &  n17(9 downto 9) &  n17(8 downto 8) &  n17(7 downto 7);process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n19 <= "00000000";    elsif i4 = "1" then      n19 <= n18;    end if;  end if;end process;n20 <= n16 - n19;process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n21 <= "00000000";    elsif i4 = "1" then      n21 <= n20;    end if;  end if;end process;n22 <= unsigned(signed(n5) * signed(n13));n23 <= n22(14 downto 14) &  n22(13 downto 13) &  n22(12 downto 12) &  n22(11 downto 11) &  n22(10 downto 10) &  n22(9 downto 9) &  n22(8 downto 8) &  n22(7 downto 7);process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n24 <= "00000000";    elsif i4 = "1" then      n24 <= n23;    end if;  end if;end process;n25 <= unsigned(signed(n6) * signed(n12));n26 <= n25(14 downto 14) &  n25(13 downto 13) &  n25(12 downto 12) &  n25(11 downto 11) &  n25(10 downto 10) &  n25(9 downto 9) &  n25(8 downto 8) &  n25(7 downto 7);process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n27 <= "00000000";    elsif i4 = "1" then      n27 <= n26;    end if;  end if;end process;n28 <= n24 + n27;process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n29 <= "00000000";    elsif i4 = "1" then      n29 <= n28;    end if;  end if;end process;n30 <= n8 + n21;n31 <= n10 + n29;n32 <= n30 & n31;process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n33 <= "0000000000000000";    elsif i4 = "1" then      n33 <= n32;    end if;  end if;end process;n34 <= n8 - n21;n35 <= n10 - n29;n36 <= n34 & n35;process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n37 <= "0000000000000000";    elsif i4 = "1" then      n37 <= n36;    end if;  end if;end process;o2 <= n37;o1 <= n33;end architecture rtl;library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity cf_fft_1024_8_38 isport (i1 : in  unsigned(0 downto 0);i2 : in  unsigned(0 downto 0);i3 : in  unsigned(0 downto 0);i4 : in  unsigned(0 downto 0);i5 : in  unsigned(2 downto 0);o1 : out unsigned(0 downto 0));end entity cf_fft_1024_8_38;architecture rtl of cf_fft_1024_8_38 issignal n1 : unsigned(2 downto 0);signal n2 : unsigned(2 downto 0);signal n3 : unsigned(2 downto 0);signal n4 : unsigned(0 downto 0);signal n5 : unsigned(0 downto 0);signal n6 : unsigned(0 downto 0);signal n7 : unsigned(0 downto 0);signal n8 : unsigned(0 downto 0);signal n9 : unsigned(0 downto 0);beginn1 <= "001";n2 <= "011";n3 <= "101";n4 <= "1" when i5 = n1 else "0";n5 <= "1" when i5 = n2 else "0";n6 <= "1" when i5 = n3 else "0";n7 <= i2 when n6 = "1" else i1;n8 <= i3 when n5 = "1" else n7;n9 <= i4 when n4 = "1" else n8;o1 <= n9;end architecture rtl;library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity cf_fft_1024_8_37 isport (i1 : in  unsigned(0 downto 0);i2 : in  unsigned(0 downto 0);i3 : in  unsigned(0 downto 0);i4 : in  unsigned(0 downto 0);i5 : in  unsigned(0 downto 0);i6 : in  unsigned(0 downto 0);i7 : in  unsigned(0 downto 0);i8 : in  unsigned(2 downto 0);o1 : out unsigned(0 downto 0));end entity cf_fft_1024_8_37;architecture rtl of cf_fft_1024_8_37 is