input  i4;input  i5;output o1;output [15:0] o2;output [15:0] o3;wire   [1:0] n1;wire   [31:0] n2;reg    n3;reg    n4;reg    n5;reg    n6;wire   [7:0] n7;reg    [7:0] n8;reg    [7:0] n9;reg    [7:0] n10;reg    [7:0] n11;wire   n12;reg    n13;reg    n14;reg    n15;reg    n16;wire   n17;wire   [1:0] n18;wire   [15:0] n19;wire   [15:0] n20;wire   [15:0] n21;wire   [15:0] n22;wire   [15:0] n23;wire   [15:0] n24;wire   [15:0] s25_1;wire   [15:0] s25_2;wire   s26_1;wire   s27_1;wire   s27_2;wire   [31:0] s27_3;wire   [31:0] s28_1;wire   [8:0] s29_1;wire   s29_2;assign n1 = {s29_1[8],  s29_1[7]};assign n2 = {s25_1, s25_2};initial n3 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n3 <= 1'b0;  else if (i4 == 1'b1)    n3 <= s29_2;initial n4 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n4 <= 1'b0;  else if (i4 == 1'b1)    n4 <= n3;initial n5 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n5 <= 1'b0;  else if (i4 == 1'b1)    n5 <= n4;initial n6 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n6 <= 1'b0;  else if (i4 == 1'b1)    n6 <= n5;assign n7 = {s29_1[8],  s29_1[7],  s29_1[6],  s29_1[5],  s29_1[4],  s29_1[3],  s29_1[2],  s29_1[1]};initial n8 = 8'b00000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n8 <= 8'b00000000;  else if (i4 == 1'b1)    n8 <= n7;initial n9 = 8'b00000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n9 <= 8'b00000000;  else if (i4 == 1'b1)    n9 <= n8;initial n10 = 8'b00000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n10 <= 8'b00000000;  else if (i4 == 1'b1)    n10 <= n9;initial n11 = 8'b00000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n11 <= 8'b00000000;  else if (i4 == 1'b1)    n11 <= n10;assign n12 = s29_1[0];initial n13 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n13 <= 1'b0;  else if (i4 == 1'b1)    n13 <= n12;initial n14 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n14 <= 1'b0;  else if (i4 == 1'b1)    n14 <= n13;initial n15 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n15 <= 1'b0;  else if (i4 == 1'b1)    n15 <= n14;initial n16 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n16 <= 1'b0;  else if (i4 == 1'b1)    n16 <= n15;assign n17 = ~n16;assign n18 = {s27_2, s27_1};assign n19 = {s27_3[31],  s27_3[30],  s27_3[29],  s27_3[28],  s27_3[27],  s27_3[26],  s27_3[25],  s27_3[24],  s27_3[23],  s27_3[22],  s27_3[21],  s27_3[20],  s27_3[19],  s27_3[18],  s27_3[17],  s27_3[16]};assign n20 = {s27_3[15],  s27_3[14],  s27_3[13],  s27_3[12],  s27_3[11],  s27_3[10],  s27_3[9],  s27_3[8],  s27_3[7],  s27_3[6],  s27_3[5],  s27_3[4],  s27_3[3],  s27_3[2],  s27_3[1],  s27_3[0]};assign n21 = {s28_1[31],  s28_1[30],  s28_1[29],  s28_1[28],  s28_1[27],  s28_1[26],  s28_1[25],  s28_1[24],  s28_1[23],  s28_1[22],  s28_1[21],  s28_1[20],  s28_1[19],  s28_1[18],  s28_1[17],  s28_1[16]};assign n22 = {s28_1[15],  s28_1[14],  s28_1[13],  s28_1[12],  s28_1[11],  s28_1[10],  s28_1[9],  s28_1[8],  s28_1[7],  s28_1[6],  s28_1[5],  s28_1[4],  s28_1[3],  s28_1[2],  s28_1[1],  s28_1[0]};assign n23 = s26_1 ? n20 : n19;assign n24 = s26_1 ? n22 : n21;cf_fft_1024_8_8 s25 (clock_c, i2, i3, n1, i4, i5, s25_1, s25_2);cf_fft_1024_8_33 s26 (clock_c, n18, i4, i5, s26_1);cf_fft_1024_8_28 s27 (clock_c, n2, n6, n11, n17, i4, i5, s27_1, s27_2, s27_3);cf_fft_1024_8_29 s28 (clock_c, n2, n6, n11, n16, i4, i5, s28_1);cf_fft_1024_8_24 s29 (clock_c, i1, i4, i5, s29_1, s29_2);assign o3 = n24;assign o2 = n23;assign o1 = s27_1;endmodulemodule cf_fft_1024_8_8 (clock_c, i1, i2, i3, i4, i5, o1, o2);input  clock_c;input  [15:0] i1;input  [15:0] i2;input  [1:0] i3;input  i4;input  i5;output [15:0] o1;output [15:0] o2;reg    [15:0] n1;wire   [7:0] n2;wire   [7:0] n3;reg    [15:0] n4;wire   [7:0] n5;wire   [7:0] n6;reg    [7:0] n7;reg    [7:0] n8;reg    [7:0] n9;reg    [7:0] n10;reg    [15:0] n11;wire   [7:0] n12;wire   [7:0] n13;wire   [15:0] n14;wire   [7:0] n15;reg    [7:0] n16;wire   [15:0] n17;wire   [7:0] n18;reg    [7:0] n19;wire   [7:0] n20;reg    [7:0] n21;wire   [15:0] n22;wire   [7:0] n23;reg    [7:0] n24;wire   [15:0] n25;wire   [7:0] n26;reg    [7:0] n27;wire   [7:0] n28;reg    [7:0] n29;wire   [7:0] n30;wire   [7:0] n31;wire   [15:0] n32;reg    [15:0] n33;wire   [7:0] n34;wire   [7:0] n35;wire   [15:0] n36;reg    [15:0] n37;initial n1 = 16'b0000000000000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n1 <= 16'b0000000000000000;  else if (i4 == 1'b1)    n1 <= i1;assign n2 = {n1[15],  n1[14],  n1[13],  n1[12],  n1[11],  n1[10],  n1[9],  n1[8]};assign n3 = {n1[7],  n1[6],  n1[5],  n1[4],  n1[3],  n1[2],  n1[1],  n1[0]};initial n4 = 16'b0000000000000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n4 <= 16'b0000000000000000;  else if (i4 == 1'b1)    n4 <= i2;assign n5 = {n4[15],  n4[14],  n4[13],  n4[12],  n4[11],  n4[10],  n4[9],  n4[8]};assign n6 = {n4[7],  n4[6],  n4[5],  n4[4],  n4[3],  n4[2],  n4[1],  n4[0]};initial n7 = 8'b00000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n7 <= 8'b00000000;  else if (i4 == 1'b1)    n7 <= n2;initial n8 = 8'b00000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n8 <= 8'b00000000;  else if (i4 == 1'b1)    n8 <= n7;initial n9 = 8'b00000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n9 <= 8'b00000000;  else if (i4 == 1'b1)    n9 <= n3;initial n10 = 8'b00000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n10 <= 8'b00000000;  else if (i4 == 1'b1)    n10 <= n9;initial n11 = 16'b0000000000000000;always @ (posedge clock_c)  if (i4 == 1'b1)    case (i3)      2'b00 : n11 <= 16'b0111111100000000;      2'b01 : n11 <= 16'b0101101010100101;      2'b10 : n11 <= 16'b0000000010000000;      2'b11 : n11 <= 16'b1010010110100101;      default : n11 <= 16'bxxxxxxxxxxxxxxxx;    endcaseassign n12 = {n11[15],  n11[14],  n11[13],  n11[12],  n11[11],  n11[10],  n11[9],  n11[8]};assign n13 = {n11[7],  n11[6],  n11[5],  n11[4],  n11[3],  n11[2],  n11[1],  n11[0]};assign n14 = {{8{n5[7]}}, n5} * {{8{n12[7]}}, n12};assign n15 = {n14[14],  n14[13],  n14[12],  n14[11],  n14[10],  n14[9],  n14[8],  n14[7]};initial n16 = 8'b00000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n16 <= 8'b00000000;  else if (i4 == 1'b1)    n16 <= n15;assign n17 = {{8{n6[7]}}, n6} * {{8{n13[7]}}, n13};assign n18 = {n17[14],  n17[13],  n17[12],  n17[11],  n17[10],  n17[9],  n17[8],  n17[7]};initial n19 = 8'b00000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n19 <= 8'b00000000;  else if (i4 == 1'b1)    n19 <= n18;assign n20 = n16 - n19;initial n21 = 8'b00000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n21 <= 8'b00000000;  else if (i4 == 1'b1)    n21 <= n20;assign n22 = {{8{n5[7]}}, n5} * {{8{n13[7]}}, n13};assign n23 = {n22[14],  n22[13],  n22[12],  n22[11],  n22[10],  n22[9],  n22[8],  n22[7]};initial n24 = 8'b00000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n24 <= 8'b00000000;  else if (i4 == 1'b1)    n24 <= n23;assign n25 = {{8{n6[7]}}, n6} * {{8{n12[7]}}, n12};assign n26 = {n25[14],  n25[13],  n25[12],  n25[11],  n25[10],  n25[9],  n25[8],  n25[7]};initial n27 = 8'b00000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n27 <= 8'b00000000;  else if (i4 == 1'b1)    n27 <= n26;assign n28 = n24 + n27;initial n29 = 8'b00000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n29 <= 8'b00000000;  else if (i4 == 1'b1)    n29 <= n28;assign n30 = n8 + n21;assign n31 = n10 + n29;assign n32 = {n30, n31};initial n33 = 16'b0000000000000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n33 <= 16'b0000000000000000;  else if (i4 == 1'b1)    n33 <= n32;assign n34 = n8 - n21;assign n35 = n10 - n29;assign n36 = {n34, n35};initial n37 = 16'b0000000000000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n37 <= 16'b0000000000000000;  else if (i4 == 1'b1)    n37 <= n36;assign o2 = n37;assign o1 = n33;endmodulemodule cf_fft_1024_8_9 (clock_c, i1, i2, i3, i4, i5, o1, o2, o3);input  clock_c;input  i1;input  [15:0] i2;input  [15:0] i3;input  i4;input  i5;output o1;output [15:0] o2;output [15:0] o3;wire   [2:0] n1;wire   [31:0] n2;reg    n3;reg    n4;reg    n5;reg    n6;wire   [7:0] n7;reg    [7:0] n8;reg    [7:0] n9;reg    [7:0] n10;reg    [7:0] n11;wire   n12;reg    n13;reg    n14;reg    n15;reg    n16;wire   n17;wire   [1:0] n18;wire   [15:0] n19;wire   [15:0] n20;wire   [15:0] n21;wire   [15:0] n22;wire   [15:0] n23;wire   [15:0] n24;wire   s25_1;wire   [15:0] s26_1;wire   [15:0] s26_2;wire   [8:0] s27_1;wire   s27_2;wire   s28_1;wire   s28_2;wire   [31:0] s28_3;wire   [31:0] s29_1;assign n1 = {s27_1[8],  s27_1[7],  s27_1[6]};assign n2 = {s26_1, s26_2};initial n3 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n3 <= 1'b0;  else if (i4 == 1'b1)    n3 <= s27_2;initial n4 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n4 <= 1'b0;  else if (i4 == 1'b1)    n4 <= n3;initial n5 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n5 <= 1'b0;  else if (i4 == 1'b1)    n5 <= n4;initial n6 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n6 <= 1'b0;  else if (i4 == 1'b1)    n6 <= n5;assign n7 = {s27_1[8],  s27_1[7],  s27_1[6],  s27_1[5],  s27_1[4],  s27_1[3],  s27_1[2],  s27_1[1]};initial n8 = 8'b00000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n8 <= 8'b00000000;  else if (i4 == 1'b1)    n8 <= n7;initial n9 = 8'b00000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n9 <= 8'b00000000;  else if (i4 == 1'b1)    n9 <= n8;initial n10 = 8'b00000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n10 <= 8'b00000000;  else if (i4 == 1'b1)    n10 <= n9;initial n11 = 8'b00000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n11 <= 8'b00000000;  else if (i4 == 1'b1)    n11 <= n10;assign n12 = s27_1[0];initial n13 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n13 <= 1'b0;  else if (i4 == 1'b1)    n13 <= n12;initial n14 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n14 <= 1'b0;  else if (i4 == 1'b1)    n14 <= n13;initial n15 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n15 <= 1'b0;  else if (i4 == 1'b1)    n15 <= n14;initial n16 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n16 <= 1'b0;  else if (i4 == 1'b1)    n16 <= n15;assign n17 = ~n16;assign n18 = {s28_2, s28_1};assign n19 = {s28_3[31],  s28_3[30],  s28_3[29],  s28_3[28],  s28_3[27],  s28_3[26],  s28_3[25],  s28_3[24],  s28_3[23],  s28_3[22],  s28_3[21],  s28_3[20],  s28_3[19],  s28_3[18],  s28_3[17],  s28_3[16]};assign n20 = {s28_3[15],  s28_3[14],  s28_3[13],  s28_3[12],  s28_3[11],  s28_3[10],  s28_3[9],  s28_3[8],  s28_3[7],  s28_3[6],  s28_3[5],  s28_3[4],  s28_3[3],  s28_3[2],  s28_3[1],  s28_3[0]};assign n21 = {s29_1[31],  s29_1[30],  s29_1[29],  s29_1[28],  s29_1[27],  s29_1[26],  s29_1[25],  s29_1[24],  s29_1[23],  s29_1[22],  s29_1[21],  s29_1[20],  s29_1[19],  s29_1[18],  s29_1[17],  s29_1[16]};assign n22 = {s29_1[15],  s29_1[14],  s29_1[13],  s29_1[12],  s29_1[11],  s29_1[10],  s29_1[9],  s29_1[8],  s29_1[7],  s29_1[6],  s29_1[5],  s29_1[4],  s29_1[3],  s29_1[2],  s29_1[1],  s29_1[0]};assign n23 = s25_1 ? n20 : n19;assign n24 = s25_1 ? n22 : n21;cf_fft_1024_8_33 s25 (clock_c, n18, i4, i5, s25_1);cf_fft_1024_8_10 s26 (clock_c, i2, i3, n1, i4, i5, s26_1, s26_2);cf_fft_1024_8_24 s27 (clock_c, i1, i4, i5, s27_1, s27_2);cf_fft_1024_8_28 s28 (clock_c, n2, n6, n11, n17, i4, i5, s28_1, s28_2, s28_3);cf_fft_1024_8_29 s29 (clock_c, n2, n6, n11, n16, i4, i5, s29_1);assign o3 = n24;assign o2 = n23;assign o1 = s28_1;endmodulemodule cf_fft_1024_8_10 (clock_c, i1, i2, i3, i4, i5, o1, o2);input  clock_c;