.module ytcpg01.c
	.area data(ram, con, rel)
_tmpRx::
	.blkb 1
	.area idata
	.byte 0
	.area data(ram, con, rel)
	.dbfile E:\job\elite\云臺控制器\avr\ytcpg01.c
	.dbsym e tmpRx _tmpRx c
_RXCR::
	.blkb 1
	.area idata
	.byte 0
	.area data(ram, con, rel)
	.dbfile E:\job\elite\云臺控制器\avr\ytcpg01.c
	.dbsym e RXCR _RXCR c
_RXstartFlag::
	.blkb 1
	.area idata
	.byte 0
	.area data(ram, con, rel)
	.dbfile E:\job\elite\云臺控制器\avr\ytcpg01.c
	.dbsym e RXstartFlag _RXstartFlag c
	.area text(rom, con, rel)
	.dbfile E:\job\elite\云臺控制器\avr\ytcpg01.c
	.dbfunc e watchdog_init _watchdog_init fV
	.even
_watchdog_init::
	.dbline -1
	.dbline 51
; //update on 2004-04-22 21:45 
; //chage Level check : DBNEW
; // deal with rotory speed unsteable
; 
; 
; //one charter a to send
; #include <iom8515v.h>
; #include <macros.h>
; #include <eeprom.h>
; 
; //outport define
; #define OUTau8ON PORTC|=0x01
; #define OUTau8OFF PORTC&=~0x01        
; #define OUTau7ON PORTC|=0x02
; #define OUTau7OFF PORTC&=~0x02
; #define OUTau6ON PORTC|=0x04
; #define OUTau6OFF PORTC&=~0x04        
; #define OUTau5ON PORTC|=0x08
; #define OUTau5OFF PORTC&=~0x08
; #define OUTau4ON PORTC|=0x10
; #define OUTau4OFF PORTC&=~0x10        
; #define OUTau3ON PORTC|=0x20
; #define OUTau3OFF PORTC&=~0x20
; #define OUTau2ON PORTC|=0x40
; #define OUTau2OFF PORTC&=~0x40        
; #define OUTau1ON PORTC|=0x80
; #define OUTau1OFF PORTC&=~0x80
; #define OUTau1Pulse PORTC^=0x80
;     
; #define CLROFF PORTB|=0x01
; #define CLRON PORTB&=~0x01
; 
; #define BOARDID '1'
; 
; //全局變量
; unsigned char OPDATA[12];
; 
; 
; unsigned char TXbuf[18];
; unsigned char RXbuf[18];
; unsigned char tmpRx=0;
; unsigned char RXCR=0;
; unsigned char RXstartFlag=0;
; 
; union mdd {
;            unsigned int TXCRC;
; 		   unsigned char txCRC[2];
;           }CRCT;
; 
; void watchdog_init(void)
;      {
	.dbline 52
; 	   WDR();
	wdr
	.dbline 53
; 	   WDTCR=0x0F ;
	ldi R24,15
	out 0x21,R24
	.dbline -2
L1:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e Delay_1ms _Delay_1ms fV
;              i -> R16,R17
	.even
_Delay_1ms::
	.dbline -1
	.dbline 57
; 	 }
; 	 
; void Delay_1ms(void)
; 	{
	.dbline 60
; 	unsigned int i;
; 
; 	for (i = 1; i<1140; i++)
	ldi R16,1
	ldi R17,0
	rjmp L6
L3:
	.dbline 62
L4:
	.dbline 60
	subi R16,255  ; offset = 1
	sbci R17,255
L6:
	.dbline 60
	cpi R16,116
	ldi R30,4
	cpc R17,R30
	brlo L3
	.dbline -2
L2:
	.dbline 0 ; func end
	ret
	.dbsym r i 16 i
	.dbend
	.dbfunc e delayXms _delayXms fV
;              i -> R20,R21
;              n -> R22,R23
	.even
_delayXms::
	rcall push_gset2
	movw R22,R16
	.dbline -1
	.dbline 66
; 		
; 			;
; 	}
; 
; void delayXms(unsigned int n)
;      {
	.dbline 67
; 	   unsigned int i=0;
	clr R20
	clr R21
	rjmp L9
L8:
	.dbline 69
	.dbline 70
	rcall _Delay_1ms
	.dbline 71
	subi R20,255  ; offset = 1
	sbci R21,255
	.dbline 72
L9:
	.dbline 68
; 	   while(i<n)
	cp R20,R22
	cpc R21,R23
	brlo L8
	.dbline -2
L7:
	rcall pop_gset2
	.dbline 0 ; func end
	ret
	.dbsym r i 20 i
	.dbsym r n 22 i
	.dbend
	.dbfunc e port_init _port_init fV
	.even
_port_init::
	.dbline -1
	.dbline 76
; 	     {
; 		  Delay_1ms();
; 		  i++;
; 		 }
; 	 }
; 	 
; void port_init(void)
;      {
	.dbline 77
; 	  PORTA=0xF0;    //PA set to 1
	ldi R24,240
	out 0x1b,R24
	.dbline 78
; 	  DDRA=0xF0;     //PA0-PA3:ADC PA4-PA6:KL0-KL2(OUT)
	out 0x1a,R24
	.dbline 81
; 	                 //PA7:LCD-E  (OUTPUT)
; 					 
; 	  PORTB=0xFF;    //PB set to 1
	ldi R24,255
	out 0x18,R24
	.dbline 82
; 	  DDRB=0xFF;     //PB0-PB2:QN0-QN2    PB3:TEMPC(OUT)
	out 0x17,R24
	.dbline 85
; 	                 //PB4-PB7:KR0-KR3(IN)
; 					 
; 	  PORTC=0x00;    //PC set to 1
	clr R2
	out 0x15,R2
	.dbline 86
; 	  DDRC=0xFF;     //PC0-PC7:DB0-DB7
	out 0x14,R24
	.dbline 88
; 	      
; 	  PORTD=0x00;    //PD set to 1
	out 0x12,R2
	.dbline 89
; 	  DDRD=0x02;     
	ldi R24,2
	out 0x11,R24
	.dbline 92
; 	  //OUTDEON;
; 	  
; 	SFIOR&=~(1<<PUD);  //OPEN UP LINK
	in R24,0x30
	andi R24,251
	out 0x30,R24
	.dbline -2
L11:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e SPI_MasterInit _SPI_MasterInit fV
	.even
_SPI_MasterInit::
	.dbline -1
	.dbline 98
; 	  
; 	  //delayXms(2000); //delay 1s
; 	 }
; 	 
; void SPI_MasterInit(void)
;      {
	.dbline 100
; 	  //SPCR=0xD1; //SPIE ,SPE ,Master enable ;1/16 Fcl
; 	  SPCR=0x51;  // ,SPE ,Master enable ;1/16 Fcl
	ldi R24,81
	out 0xd,R24
	.dbline -2
L12:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e SPI_Tran _SPI_Tran fV
;              i -> R16
	.even
_SPI_Tran::
	.dbline -1
	.dbline 103
; 	 }
; void SPI_Tran(void)
;  {
	.dbline 105
;   unsigned char i;
;  for(i=8;i>0;i--)
	ldi R16,8
	rjmp L17
L14:
	.dbline 106
;  {
	.dbline 107
;   SPDR=OPDATA[i];
	ldi R24,<_OPDATA
	ldi R25,>_OPDATA
	mov R30,R16
	clr R31
	add R30,R24
	adc R31,R25
	ldd R2,z+0
	out 0xf,R2
L18:
	.dbline 108
L19:
	.dbline 108
	sbis 0xe,7
	rjmp L18
	.dbline 109
L15:
	.dbline 105
	dec R16
L17:
	.dbline 105
	clr R2
	cp R2,R16
	brlo L14
	.dbline -2
L13:
	.dbline 0 ; func end
	ret
	.dbsym r i 16 c
	.dbend
	.dbfunc e uart_init _uart_init fV
	.even
_uart_init::
	.dbline -1
	.dbline 117
;   while(!(SPSR&0x80));
;  }
;   //delayXms(1);
;   
;  }//unsigned
;  
;  
; 
;  void uart_init(void) 
;    {
	.dbline 118
;     UCSRB=0x00;
	clr R2
	out 0xa,R2
	.dbline 119
; 	UBRR=0x33;  //9600bps
	ldi R24,51
	out 0x9,R24
	.dbline 121
; 	//UCR=0xd8;
; 	UCSRB=(1<<RXCIE)|(1<<RXEN)|(1<<TXEN);
	ldi R24,152
	out 0xa,R24
	.dbline 122
; 	UCSRC=(1<<URSEL)|(1<<UCSZ1)|(1<<UCSZ0);
	ldi R24,134
	out 0x20,R24
	.dbline -2
L21:
	.dbline 0 ; func end
	ret
	.dbend
	.area vector(rom, abs)
	.org 22
	rjmp _uart0_tx_isr
	.area text(rom, con, rel)
	.dbfile E:\job\elite\云臺控制器\avr\ytcpg01.c
	.dbfunc e uart0_tx_isr _uart0_tx_isr fV
	.even
_uart0_tx_isr::
	.dbline -1
	.dbline 128
;    }
;    
;    
;  #pragma interrupt_handler uart0_tx_isr:12
;   void uart0_tx_isr(void)
;     {
	.dbline 129
; 	;
	.dbline -2
L22:
	.dbline 0 ; func end
	reti
	.dbend
	.area vector(rom, abs)
	.org 18
	rjmp _uart0_rx_isr
	.area text(rom, con, rel)
	.dbfile E:\job\elite\云臺控制器\avr\ytcpg01.c
	.dbfunc e uart0_rx_isr _uart0_rx_isr fV
;              i -> R20
	.even
_uart0_rx_isr::
	rcall push_lset
	rcall push_gset1
	.dbline -1
	.dbline 135
; 	  
; 	}
; 
; #pragma interrupt_handler uart0_rx_isr:10
;   void uart0_rx_isr(void)
;     {	
	.dbline 139
; 	
; 	unsigned char i;
; 	//SEI();
; 	tmpRx=UDR;
	in R2,0xc
	sts _tmpRx,R2
	.dbline 145
; 	////while(!(UCSRA & (1<<UDRE)))
; 	//// ;
; 	////UDR=tmpRx;  //TX the data of rx
; 	
; 	//OUTrunON;
; 	if (tmpRx=='%')
	mov R24,R2
	cpi R24,37
	brne L24
	.dbline 146
; 	   {
	.dbline 149
; 	   
; 	   //PORTC=0xff;
; 	    RXCR=0;		
	clr R2
	sts _RXCR,R2
	.dbline 150
; 		RXstartFlag=1;
	ldi R24,1
	sts _RXstartFlag,R24
	.dbline 151
; 	   }//if tmprx	  
L24:
	.dbline 153
; 	 
; 	 if (RXCR>16) 
	ldi R24,16
	lds R2,_RXCR
	cp R24,R2
	brsh L26
	.dbline 154
; 	   {
	.dbline 155
; 	     RXCR=0;
	clr R2
	sts _RXCR,R2
	.dbline 157
; 		 //
; 	   }
L26:
	.dbline 159
; 	  
; 	 RXbuf[RXCR]=tmpRx;	
	ldi R24,<_RXbuf
	ldi R25,>_RXbuf
	lds R30,_RXCR
	clr R31
	add R30,R24
	adc R31,R25
	lds R2,_tmpRx
	std z+0,R2
	.dbline 160
; 	 RXCR++; 
	lds R24,_RXCR
	subi R24,255    ; addi 1
	sts _RXCR,R24
	.dbline 163
; 	 //SEI();
; 	 
; 	if(RXstartFlag==1 && RXCR==15 && RXbuf[0]=='%')
	lds R24,_RXstartFlag
	cpi R24,1
	breq X1
	rjmp L28
X1:
	lds R24,_RXCR
	cpi R24,15
	breq X2
	rjmp L28
X2:
	lds R24,_RXbuf
	cpi R24,37
	breq X3
	rjmp L28
X3:
	.dbline 164
; 	  {	
	.dbline 165
; 	  RXstartFlag=0;
	clr R2
	sts _RXstartFlag,R2
	.dbline 167
; 	// OUTau1Pulse;
; 	   if(RXbuf[1]==BOARDID && RXbuf[14]=='$')
	lds R24,_RXbuf+1
	cpi R24,49
	breq X4
	rjmp L30
X4:
	lds R24,_RXbuf+14
	cpi R24,36
	breq X5
	rjmp L30
X5:
	.dbline 169
; 	  //if(RXbuf[1]==BOARDID)
; 	     {
	.dbline 171
; 		 //OUTau1Pulse;
; 		 CRCT.TXCRC=0;
	clr R3
	sts _CRCT+1,R3
	sts _CRCT,R2
	.dbline 172
; 		 for(i=0;i<12;i++)
	clr R20
	rjmp L37
L34:
	.dbline 173
	.dbline 174
	ldi R24,<_RXbuf
	ldi R25,>_RXbuf
	mov R30,R20
	clr R31
	add R30,R24
	adc R31,R25
	ldd R2,z+0
	clr R3
	lds R4,_CRCT
	lds R5,_CRCT+1
	add R4,R2
	adc R5,R3
	sts _CRCT+1,R5
	sts _CRCT,R4
	.dbline 175
L35:
	.dbline 172
	inc R20
L37:
	.dbline 172
	cpi R20,12
	brlo L34
	.dbline 177
; 		{
; 		 CRCT.TXCRC=CRCT.TXCRC+RXbuf[i];
; 		}//for(i=0;i<12;i++)
; 		
; 		 if(CRCT.txCRC[0]==RXbuf[12] && CRCT.txCRC[1]==RXbuf[13])
	lds R2,_RXbuf+12
	lds R3,_CRCT
	cp R3,R2
	breq X6
	rjmp L38
X6:
	lds R2,_RXbuf+13
	lds R3,_CRCT+1
	cp R3,R2
	brne L38
	.dbline 178
; 		  {
	.dbline 179
; 		  if(RXbuf[2]=='1')
	lds R24,_RXbuf+2
	cpi R24,49
	brne L43
	.dbline 180
; 		    {
	.dbline 182
; 		     
; 			 for(i=3;i<12;i++)
	ldi R20,3
	rjmp L49
L46:
	.dbline 183
	.dbline 184
	ldi R24,<_RXbuf
	ldi R25,>_RXbuf
	mov R30,R20
	clr R31
	add R30,R24
	adc R31,R25
	ldd R2,z+0
	ldi R24,<_OPDATA-3
	ldi R25,>_OPDATA-3
	mov R30,R20
	clr R31
	add R30,R24
	adc R31,R25
	std z+0,R2
	.dbline 185
L47:
	.dbline 182
	inc R20
L49:
	.dbline 182
	cpi R20,12
	brlo L46
	.dbline 187
; 			    {
; 				  OPDATA[i-3]=RXbuf[i];
; 				}//for(i=2;i<10;i++)
; 				
; 			PORTC=OPDATA[0];
	lds R2,_OPDATA
	out 0x15,R2
	.dbline 188
; 			SPI_Tran();
	rcall _SPI_Tran
	.dbline 189
; 	        }//if(RXbuf[2]=='1')
L43:
	.dbline 192
; 			
; 			//ANSWER
; 			TXbufINIT();
	rcall _TXbufINIT
	.dbline 193
; 			for (i=0;i<15;i++)
	clr R20
	rjmp L54
X0:
	.dbline 194
; 			  {
L55:
	.dbline 196
L56:
	.dbline 195
	sbis 0xb,5
	rjmp L55
	.dbline 197
	ldi R24,<_TXbuf
	ldi R25,>_TXbuf
	mov R30,R20
	clr R31
	add R30,R24
	adc R31,R25
	ldd R2,z+0
	out 0xc,R2
	.dbline 198
L52:
	.dbline 193
	inc R20
L54:
	.dbline 193
	cpi R20,15
	brlo L56
	.dbline 200
; 			   while(!(UCSRA & (1<<UDRE)))
; 	            ;
; 	          UDR=TXbuf[i];  //TX the data of rx
; 			 }//for (i=0;i<15;i++)
; 		   
; 		 }//if(CRCT.txCRC[0]==RXbuf[12] && CRCT.txCRC[1]==RXbuf[13]) 
L38:
	.dbline 203
; 		 
; 		  
; 	   }//if(RXbuf[1]==BOARDID && RXbuf[12]=='$')
L30:
	.dbline 205
	clr R2
	sts _RXbuf,R2
	.dbline 206
	sts _RXbuf+1,R2
	.dbline 207
	sts _RXbuf+14,R2
	.dbline 208
L28:
	.dbline -2
L23:
	rcall pop_gset1
	rcall pop_lset
	.dbline 0 ; func end
	reti
	.dbsym r i 20 c
	.dbend
	.dbfunc e TXbufINIT _TXbufINIT fV
;              i -> R16
	.even
_TXbufINIT::
	.dbline -1
	.dbline 214
; 	   
; 	   RXbuf[0]=0;
; 	   RXbuf[1]=0;
; 	   RXbuf[14]=0;
; 	  } //if(RXstartFlag==1 && RXCR==13 && RXbuf[0]=='%')
; 	
; 	} //void 
;  
;  
; void TXbufINIT(void)
;      {
	.dbline 217
; 	 
; 	 unsigned char i;
; 	 TXbuf[0]=37;
	ldi R24,37
	sts _TXbuf,R24
	.dbline 218
; 	 TXbuf[1]=49;
	ldi R24,49
	sts _TXbuf+1,R24
	.dbline 219
; 	 TXbuf[2]=49;
	sts _TXbuf+2,R24
	.dbline 220
; 	 TXbuf[14]=36;
	ldi R24,36
	sts _TXbuf+14,R24
	.dbline 221
; 	  for(i=3;i<12;i++)
	ldi R16,3
	rjmp L67
L64:
	.dbline 222
	.dbline 223
	ldi R24,<_OPDATA-3
	ldi R25,>_OPDATA-3
	mov R30,R16
	clr R31
	add R30,R24
	adc R31,R25
	ldd R2,z+0
	ldi R24,<_TXbuf
	ldi R25,>_TXbuf
	mov R30,R16
	clr R31
	add R30,R24
	adc R31,R25
	std z+0,R2
	.dbline 224
L65:
	.dbline 221
	inc R16
L67:
	.dbline 221
	cpi R16,12
	brlo L64
	.dbline 225
; 		{
; 		 TXbuf[i]=OPDATA[i-3];
; 		}//for(i=2;i<10;i++)
; 	 CRCT.TXCRC=0;
	clr R2
	clr R3
	sts _CRCT+1,R3
	sts _CRCT,R2
	.dbline 226
; 	 for(i=0;i<12;i++)
	clr R16
	rjmp L72
L69:
	.dbline 227
	.dbline 228
	ldi R24,<_TXbuf
	ldi R25,>_TXbuf
	mov R30,R16
	clr R31
	add R30,R24
	adc R31,R25
	ldd R2,z+0
	clr R3
	lds R4,_CRCT
	lds R5,_CRCT+1
	add R4,R2
	adc R5,R3
	sts _CRCT+1,R5
	sts _CRCT,R4
	.dbline 229
L70:
	.dbline 226
	inc R16
L72:
	.dbline 226
	cpi R16,12
	brlo L69
	.dbline 230
; 		{
; 		 CRCT.TXCRC=CRCT.TXCRC+TXbuf[i];
; 		}//f
; 	TXbuf[12]=CRCT.txCRC[0];
	lds R2,_CRCT
	sts _TXbuf+12,R2
	.dbline 231
; 	TXbuf[13]=CRCT.txCRC[1];
	lds R2,_CRCT+1
	sts _TXbuf+13,R2
	.dbline -2
L60:
	.dbline 0 ; func end
	ret
	.dbsym r i 16 c
	.dbend
	.dbfunc e main _main fV
;             ia -> R20
	.even
_main::
	.dbline -1
	.dbline 235
; 	 }
;     
; void main()
; 	{
	.dbline 237
; 	unsigned char ia;
; 	 port_init();
	rcall _port_init
	.dbline 238
; 	 SPI_MasterInit();
	rcall _SPI_MasterInit
	.dbline 239
; 	 uart_init();
	rcall _uart_init
	.dbline 243
; 	 
; 	 
; 	 
; 	 for(ia=0;ia<13;ia++)
	clr R20
	rjmp L80
L77:
	.dbline 244
	.dbline 245
	ldi R24,<_OPDATA
	ldi R25,>_OPDATA
	mov R30,R20
	clr R31
	add R30,R24
	adc R31,R25
	clr R2
	std z+0,R2
	.dbline 246
L78:
	.dbline 243
	inc R20
L80:
	.dbline 243
	cpi R20,13
	brlo L77
	.dbline 249
; 	    {
; 		OPDATA[ia]=0;
; 		}
; 	 
; 	 
; 	 CLRON;
	cbi 0x18,0
	.dbline 250
; 	 delayXms(100);
	ldi R16,100
	ldi R17,0
	rcall _delayXms
	.dbline 251
; 	 CLROFF;
	sbi 0x18,0
	.dbline 252
; 	 PORTC=0xff;
	ldi R24,255
	out 0x15,R24
	.dbline 253
; 	 delayXms(1000);
	ldi R16,1000
	ldi R17,3
	rcall _delayXms
	.dbline 254
; 	 PORTC=0;
	clr R2
	out 0x15,R2
	.dbline 255
; 	  SPI_Tran();
	rcall _SPI_Tran
	.dbline 256
; 	 delayXms(500);
	ldi R16,500
	ldi R17,1
	rcall _delayXms
	.dbline 257
; 	 SEI();
	sei
L81:
	.dbline 259
	.dbline 260
	.dbline 261
	.dbline 262
	.dbline 264
L82:
	.dbline 258
	rjmp L81
X7:
	.dbline -2
L76:
	.dbline 0 ; func end
	ret
	.dbsym r ia 20 c
	.dbend
	.area bss(ram, con, rel)
	.dbfile E:\job\elite\云臺控制器\avr\ytcpg01.c
_CRCT::
	.blkb 2
	.dbunion 0 2 mdd
	.dbfield 0 TXCRC i
	.dbfield 0 txCRC A[2:2]c
	.dbend
	.dbsym e CRCT _CRCT S[mdd]
_RXbuf::
	.blkb 18
	.dbsym e RXbuf _RXbuf A[18:18]c
_TXbuf::
	.blkb 18
	.dbsym e TXbuf _TXbuf A[18:18]c
_OPDATA::
	.blkb 12
	.dbsym e OPDATA _OPDATA A[12:12]c