`timescale 1ns / 10ps

module segment7(
    clk_i,
    nrst_i,
    bcd0_i,	//4b: bcd data input for 1th 7-segment
    bcd1_i,	//4b: bcd data input for 2th 7-segment
    bcd2_i,	//4b: bcd data input for 3th 7-segment
    bcd3_i,	//4b: bcd data input for 4th 7-segment
    seg7_o,	//7b: output of 7-segment
    seg7a_en_o,	//1b: enable of 1th 7-segment
    seg7b_en_o, //1b: enable of 2th 7-segment
    seg7c_en_o, //1b: enable of 3th 7-segment
    seg7d_en_o  //1b: enable of 4th 7-segment
);

input		clk_i;
input		nrst_i;
//input		bcd0_i;
//input		bcd1_i;
//input		bcd2_i;
//input		bcd3_i;
input	[3:0]	bcd0_i;
input	[3:0]	bcd1_i;
input	[3:0]	bcd2_i;
input	[3:0]	bcd3_i;
output	[6:0]	seg7_o;
output		seg7a_en_o;
output		seg7b_en_o;
output		seg7c_en_o;
output		seg7d_en_o;

wire	[6:0]	seg7_o;
reg	[6:0]	seg7_a;
reg	[6:0]	seg7_b;
reg	[6:0]	seg7_c;
reg	[6:0]	seg7_d;
reg		seg7a_en_o;
reg		seg7b_en_o;
reg		seg7c_en_o;
reg		seg7d_en_o;

reg	[3:0]	bcd0_lat;
reg	[3:0]	bcd1_lat;
reg	[3:0]	bcd2_lat;
reg	[3:0]	bcd3_lat;

// Output assignment
assign		seg7_o = seg7d_en_o ? ~seg7_d : 
			 seg7c_en_o ? ~seg7_c : 
			 seg7b_en_o ? ~seg7_b :
			 seg7a_en_o ? ~seg7_a : 7'b1111111;

// Buffering the bcd input
always @(posedge clk_i or negedge nrst_i)
    if (~nrst_i) begin
    	bcd0_lat <= 4'd0;
    	bcd1_lat <= 4'd0;
    	bcd2_lat <= 4'd0;
    	bcd3_lat <= 4'd0;
    end
    else begin
    	bcd0_lat <=#1 {3'b0, bcd0_i};
    	bcd1_lat <=#1 {3'b0, bcd1_i};
    	bcd2_lat <=#1 {3'b0, bcd2_i};
    	bcd3_lat <=#1 {3'b0, bcd3_i};
    end

// Shift registers for 7-segment enable
// a -> b -> c -> d -> a ....
always @(posedge clk_i or negedge nrst_i)
    if (~nrst_i) begin
    	seg7a_en_o <= 1'b1;
    	seg7b_en_o <= 1'b0;
    	seg7c_en_o <= 1'b0;
    	seg7d_en_o <= 1'b0;
    end
    else begin
    	seg7a_en_o <=#1 seg7d_en_o;
    	seg7b_en_o <=#1 seg7a_en_o;
    	seg7c_en_o <=#1 seg7b_en_o;
    	seg7d_en_o <=#1 seg7c_en_o;
    end

// Decode for 1th 7-segment
always	@(bcd0_lat)
    case(bcd0_lat)
	4'd0 : seg7_a = 7'b1000000;
	4'd1 : seg7_a = 7'b1111001;
	4'd2 : seg7_a = 7'b0100100;
	4'd3 : seg7_a = 7'b0110000;
	4'd4 : seg7_a = 7'b0011001;
	4'd5 : seg7_a = 7'b0010010;
	4'd6 : seg7_a = 7'b0000010;
	4'd7 : seg7_a = 7'b1111000;
	4'd8 : seg7_a = 7'b0000000;
	4'd9 : seg7_a = 7'b0010000;
	4'd10 : seg7_a = 7'b0001000;
	4'd11 : seg7_a = 7'b0000011;
	4'd12 : seg7_a = 7'b0100111;
	4'd13 : seg7_a = 7'b0100001;
	4'd14 : seg7_a = 7'b0000110;
	4'd15 : seg7_a = 7'b0001110;
    endcase

// Decode for 2th 7-segment
always	@(bcd1_lat)
    case(bcd1_lat)
	4'd0 : seg7_b = 7'b1000000;
	4'd1 : seg7_b = 7'b1111001;
	4'd2 : seg7_b = 7'b0100100;
	4'd3 : seg7_b = 7'b0110000;
	4'd4 : seg7_b = 7'b0011001;
	4'd5 : seg7_b = 7'b0010010;
	4'd6 : seg7_b = 7'b0000010;
	4'd7 : seg7_b = 7'b1111000;
	4'd8 : seg7_b = 7'b0000000;
	4'd9 : seg7_b = 7'b0010000;
	4'd10 : seg7_b = 7'b0001000;
	4'd11 : seg7_b = 7'b0000011;
	4'd12 : seg7_b = 7'b0100111;
	4'd13 : seg7_b = 7'b0100001;
	4'd14 : seg7_b = 7'b0000110;
	4'd15 : seg7_b = 7'b0001110;
    endcase

// Decode for 3th 7-segment
always	@(bcd2_lat)
    case(bcd2_lat)
	4'd0 : seg7_c = 7'b1000000;
	4'd1 : seg7_c = 7'b1111001;
	4'd2 : seg7_c = 7'b0100100;
	4'd3 : seg7_c = 7'b0110000;
	4'd4 : seg7_c = 7'b0011001;
	4'd5 : seg7_c = 7'b0010010;
	4'd6 : seg7_c = 7'b0000010;
	4'd7 : seg7_c = 7'b1111000;
	4'd8 : seg7_c = 7'b0000000;
	4'd9 : seg7_c = 7'b0010000;
	4'd10 : seg7_c = 7'b0001000;
	4'd11 : seg7_c = 7'b0000011;
	4'd12 : seg7_c = 7'b0100111;
	4'd13 : seg7_c = 7'b0100001;
	4'd14 : seg7_c = 7'b0000110;
	4'd15 : seg7_c = 7'b0001110;
    endcase

// Decode for 4th 7-segment
always	@(bcd3_lat)
    case(bcd3_lat)
	4'd0 : seg7_d = 7'b1000000;
	4'd1 : seg7_d = 7'b1111001;
	4'd2 : seg7_d = 7'b0100100;
	4'd3 : seg7_d = 7'b0110000;
	4'd4 : seg7_d = 7'b0011001;
	4'd5 : seg7_d = 7'b0010010;
	4'd6 : seg7_d = 7'b0000010;
	4'd7 : seg7_d = 7'b1111000;
	4'd8 : seg7_d = 7'b0000000;
	4'd9 : seg7_d = 7'b0010000;
	4'd10 : seg7_d = 7'b0001000;
	4'd11 : seg7_d = 7'b0000011;
	4'd12 : seg7_d = 7'b0100111;
	4'd13 : seg7_d = 7'b0100001;
	4'd14 : seg7_d = 7'b0000110;
	4'd15 : seg7_d = 7'b0001110;
    endcase


endmodule