/****************************************************************** MODULE:		Bt878 Decoder Interface** DESCRITPION:		Connexant Bt878 NTSC Video Decoder VxWorks*			5.4 PCI Driver and Video Processing Utilities** ORIGINAL AUTHOR:		Sam Siewert, University of Colorado, Boulder* UPDATED BY:			Zach Pfeffer, University of Colorado, Boulder* * CREATED:		May 7, 2000* MODIFIED:		June 17, 2004* * NOTES:** This code is intended to be used as driver bottom-half functions* rather than an exported top-half video driver interface.** Note that this was coded for VxWorks 5.4 for x86/PCI architecture* and assumes the pcPentium BSP PCI API.** CODE USAGE:** To test the bottom half functions, start video acquisition with:* ---------------------------------------------------------------------** 1) call to start_video()** 2) call to activate(1) for 320x240 RGB 32 bit 30 fps decoding** 3) call to set_mux(3) for external NTSC camera S-video input** 4) call to reset_status() to ensure proper sync of code and hardware** 5) repeated calls to report() to ensure frame acauisition is working*    and that errors in decoding are being handled properly.* * 6) call to start_streaming() to start up TCP client thread which will connect*    to a display server and send rgb_buffer frames.** The frame_acq_cnt should increase and that the DMA PC* should advance as well as the decoder count.** Finally try dumping a frame to the /tmp host directory with* the write_save_buffer(0) function call.** You can load a frame from the write_save_buffer(0) call with * the X-wind "xv" image processing tool.** 6) call to full_reset() to shut the bottom-half down completely.*** REVISION HISTORY AND NOTES:** Date			Update* ---------------------------------------------------------------------* May 7, 2000		Created.* March 23, 2001	Updated for VxWorks 5.4 - changed PCI interrupt*                       vector registration code.** July 2004		Built a struct array to store info about each PCI*			card of interest.** July 2004		Wrote:*				decodePIRQxRouteControlRegister*				findAndDecodePCIInterruptRoutingTable*				dumpPCIFunctionsConfigurationHeader*				dumpPCIStatusAndCommand** July 2004		Changed the way the Interrupt is specified. *			Instead of statically setting it in a global*			define it is now read from the BT878's interrupt *			line register in start_video().** July 2004		Expanded btvid_controller_config to output more*			debug information about the base address registers*			in the BT878.** July 2004			Due to incompatibilities in versions of*			Northbridge and Southbridge Intel chips*			the current code looks for and explicit *			vendor,device value in intel_pci_config. *			If it fails to find such a value it *			defaults to the old settings.*						** WARNINGS:** The only mode(s) fully supported and test to date are:* ---------------------------------------------------------------------* NTSC_320_X_240** Other modes have not been tested and may not work without modification.*** REFERENCES:** 1) Bt878 chipset documentation - available on the class WWW site: *    http://www-sgc.colorado.edu/~siewerts/ecen/hardware/pdf/** 2) Ph.D. dissertation on RT Video pipelines - available on the CU*    research WWW site: *    http://www-sgc.colorado.edu/~siewerts/research/rt.html** 3) PCI vendor and device IDs - available on class WWW site:*    http://www.datashopper.dk/~finth/pci.html*****************************************************************//* VxWorks API includes */#include "vxWorks.h"#include "stdio.h"#include "stdlib.h"#include "ioLib.h"#include "semLib.h"#include "intLib.h"#include "vmLib.h"   /* added to support */#include "iv.h"/* VxWorks 5.4 PCI driver interface includes */#include "drv/pci/pciConfigLib.h"#include "drv/pci/pciConfigShow.h"#include "drv/pci/pciHeaderDefs.h"#include "drv/pci/pciLocalBus.h"#include "drv/pci/pciIntLib.h"/* pcPentium BSP includes */#include "sysLib.h"/* Function prototypes that can be exported to top-half code */void	start_video(void);int	btvid_controller_config(void);void	connect_pci_int(int inum);void	set_mux(int mux);void	intel_pci_clear_status(void);void	initialize_frame_mc(int fsize);int	configure_ntsc(int fsize);int	decimate_frames(int count);void	disable_capture(void);void	enable_capture(void);void	vdfc_capture(void);void	vbi_capture(void);        /* vertical blanking lines */void	set_brightness(int b);void	set_contrast(int c);void	load_frame_mc(int fsize);void	full_reset(void);/* Function prototypes for bottom-half debug and development */int	btvid_probe(void);UINT	find_int_routing_table(void);void	print_mc(int mc);int	test_status(void);void	intel_pci_status(void);void	write_save_buffer(int bo);void	write_y8_save_buffer(void);UINT	check_buffers(int fsize);void	clear_buffers(int fsize);void	initialize_test_mc(void);void	load_test_mc(int mc);int	baseAddressRegisterSizeOfDecodeSpace(int);int	findAndDecodePCIInterruptRoutingTable(void);int	decodePIRQxRouteControlRegister(void);int 	dumpPCIFunctionsConfigurationHeader(void);int	dumpPCIStatusAndCommand(void);UINT    frameProcCnt = 0;int     enable_streaming=0;int     frameCopyRate = 5;int     frameProcRate = 15;extern int start_frame_tx;extern int frame_to_net(unsigned char *buffer);/* RGB color video decoder modes */#define NTSC_640_X_480	0#define NTSC_320_X_240	1#define NTSC_160_X_120	2#define NTSC_80_X_60	3/* Greyscale video decoder modes */#define NTSC_640_X_480_GS	4#define NTSC_320_X_240_GS	5#define NTSC_160_X_120_GS	6#define NTSC_80_X_60_GS		7 /* RISC DMA Engine Microcode for each decoder mode */#define TEST_MICROCODE		0#define RGB32_640x480_MICROCODE	1		#define RGB32_320x240_MICROCODE 2 /* Bt878 DMA Frame Buffering */#define NUMFRAMES	2/* PCI interrupt defines */#define INT_NUM_IRQ0	0x20/* #define BT878INT	0x09 */int BT878INT;/* PCI configuration space for Bt878 controller *//*#define BTVID_CTL_BUSNO		0x00000000#define BTVID_CTL_DEVNO 	0x00000011#define BTVID_CTL_FUNCNO 	0x00000000#define BTVID_CTL_VENDORID 	0x0000109e#define BTVID_CTL_DEVID 	0x0000036e*//* PCI configuration space for Intel PCI and APIC Devices *//*#define PCI_DEVICE_ID_INTEL_82439TX	0x7100#define PCI_DEVNO_INTEL_82439TX     	0x0#define PCI_FUNCNO_INTEL_82439TX     	0x0#define INTEL_NB_CTL_BUSNO 		0x00000000#define INTEL_NB_CTL_DEVNO 		PCI_DEVNO_INTEL_82439TX#define INTEL_NB_CTL_FUNCNO 		PCI_FUNCNO_INTEL_82439TX#define PCI_DEVICE_ID_INTEL_82371AB_0	0x7110#define PCI_DEVNO_INTEL_82371AB_0   	0x07#define PCI_FUNCNO_INTEL_82371AB_0   	0x0#define INTEL_SB_CTL_BUSNO 		0x00000000#define INTEL_SB_CTL_DEVNO 		PCI_DEVNO_INTEL_82371AB_0#define INTEL_SB_CTL_FUNCNO 		PCI_FUNCNO_INTEL_82371AB_0#define PCI_CFG_IRQ_ROUTING		0x60#define PCI_CFG_APIC_ADDR 		0x80#define PCI_CFG_LATENCY_CTL 		0x82#define PCI_CFG_ARB_CTL 		0x4f#define PCI_CFG_PCI_CTL 		0x50*//* Config for the Intel 440FX PCI set 82441FX (North Bridge) System Controller  * and 82371SB (South Bridge) System Controller*/#define INTEL_VENDOR_ID			0x8086#define PCI_DEVICE_ID_INTEL_82441FX	0x1237#define PCI_DEVICE_ID_INTEL_82371SB_0	0x7000/* Northbridge */#define PCI_CFG_PCI_CTL 		0x50/* Southbridge */#define PCI_CFG_IRQ_ROUTING		0x60#define PCI_CFG_APIC_ADDR 		0x80#define PCI_CFG_ARB_CTL 		0x4f#define PCI_CFG_LATENCY_CTL 		0x82#define PCI_CFG_IRQ_ROUTING_INTERRUPT_PIN_A		0x60#define PCI_CFG_IRQ_ROUTING_INTERRUPT_PIN_B		0x61#define PCI_CFG_IRQ_ROUTING_INTERRUPT_PIN_C		0x62#define PCI_CFG_IRQ_ROUTING_INTERRUPT_PIN_D		0x63/* Operates on Bytes only */#define PCI_CFG_IRQ_ROUTING_ENABLED(readback) 		!(readback >> 7)#define PCI_CFG_IRQ_LINE_TO_IRQ(readback) 		(readback & 0x0F)/* PCI command definitions */#define BUS_MASTER_MMIO 0x0006/* Bt878 MMIO registers - MMIO mapped through sysPhysMemDesc in   the pcPentium BSP to enable MMU access to these registers.   Please see Bt878 chipset documentation for full details. */#define BTVID_MMIO_ADDR		0x8000000#define TIMING_GEN_REG		(BTVID_MMIO_ADDR | 0x00000084)#define RESET_REG		(BTVID_MMIO_ADDR | 0x0000007C)#define INPUT_REG		(BTVID_MMIO_ADDR | 0x00000004)#define HSCALE_EVEN_MSB_REG	(BTVID_MMIO_ADDR | 0x00000020)#define HSCALE_ODD_MSB_REG	(BTVID_MMIO_ADDR | 0x000000A0)#define HSCALE_EVEN_LSB_REG	(BTVID_MMIO_ADDR | 0x00000024)#define HSCALE_ODD_LSB_REG	(BTVID_MMIO_ADDR | 0x000000A4)#define VSCALE_EVEN_MSB_REG	(BTVID_MMIO_ADDR | 0x0000004C)#define VSCALE_ODD_MSB_REG	(BTVID_MMIO_ADDR | 0x000000CC)#define VSCALE_EVEN_LSB_REG	(BTVID_MMIO_ADDR | 0x00000050)#define VSCALE_ODD_LSB_REG	(BTVID_MMIO_ADDR | 0x000000D0)#define COLOR_FORMAT_REG	(BTVID_MMIO_ADDR | 0x000000D4)#define BRIGHTNESS_REG		(BTVID_MMIO_ADDR | 0x00000028)#define CONTRAST_REG		(BTVID_MMIO_ADDR | 0x00000030)#define INT_STATUS_REG		(BTVID_MMIO_ADDR | 0x00000100)#define INT_ENABLE_REG		(BTVID_MMIO_ADDR | 0x00000104)#define DMA_CTL_REG		(BTVID_MMIO_ADDR | 0x0000010C)#define DMA_RISC_START_ADDR_REG	(BTVID_MMIO_ADDR | 0x00000114)#define DMA_RISC_PC_REG		(BTVID_MMIO_ADDR | 0x00000120)#define CAPTURE_CTL_REG		(BTVID_MMIO_ADDR | 0x000000DC)#define VBI_PACKET_SIZE_LO_REG	(BTVID_MMIO_ADDR | 0x000000E0)#define VBI_PACKET_SIZE_HI_REG	(BTVID_MMIO_ADDR | 0x000000E4)#define CAPTURE_CNT_REG		(BTVID_MMIO_ADDR | 0x000000E8)#define PLL_FREQ_LO_REG		(BTVID_MMIO_ADDR | 0x000000F0)#define PLL_FREQ_HIGH_REG	(BTVID_MMIO_ADDR | 0x000000F4)#define PLL_DIVIDER_REG		(BTVID_MMIO_ADDR | 0x000000F8)#define AGC_ADELAY_REG		(BTVID_MMIO_ADDR | 0x00000060)#define AGC_BDELAY_REG		(BTVID_MMIO_ADDR | 0x00000064)#define TEMP_DECIMATION_REG	(BTVID_MMIO_ADDR | 0x00000008)#define MSB_CROP_EVEN_REG	(BTVID_MMIO_ADDR | 0x0000000C)#define MSB_CROP_ODD_REG	(BTVID_MMIO_ADDR | 0x0000008C)#define VDELAY_LO_EVEN_REG	(BTVID_MMIO_ADDR | 0x00000090)#define VDELAY_LO_ODD_REG	(BTVID_MMIO_ADDR | 0x00000010)#define VACTIVE_LO_EVEN_REG	(BTVID_MMIO_ADDR | 0x00000014)#define VACTIVE_LO_ODD_REG	(BTVID_MMIO_ADDR | 0x00000094)#define HDELAY_LO_EVEN_REG	(BTVID_MMIO_ADDR | 0x00000018)#define HDELAY_LO_ODD_REG	(BTVID_MMIO_ADDR | 0x00000098)#define HACTIVE_LO_EVEN_REG	(BTVID_MMIO_ADDR | 0x0000001C)#define HACTIVE_LO_ODD_REG	(BTVID_MMIO_ADDR | 0x0000009C)/* Bt878 Interrupt Control Register Masks */#define MYSTERY_INT	0x00400000	/* must enable, but not sure why */#define SCERR_INT	0x00080000#define OCERR_INT	0x00040000#define PABORT_INT	0x00020000#define RIPERR_INT	0x00010000#define PPERR_INT	0x00008000#define FDSR_INT	0x00004000#define FTRGT_INT	0x00002000#define FBUS_INT	0x00001000#define RISCI_INT	0x00000800 	/* microcode frame complete int */#define VPRES_INT	0x00000020#define FMTCHG_INT	0x00000001/* Bt878 and PCI interface globals */UINT	sysVectorIRQ0		= INT_NUM_IRQ0;UINT	ir_table_addr		= NULL;UINT	frame_rdy_cnt 		= 0;int	replace_write_with_skip	= FALSE;int	acq_type		= NTSC_320_X_240;UINT	int_errors_to_check = (				SCERR_INT	|				OCERR_INT	|                                PABORT_INT	|                                RIPERR_INT	|                                PPERR_INT	|                                FDSR_INT	|                                FTRGT_INT	|                                FBUS_INT	|                                MYSTERY_INT);STATUS  pciLibInitStatus = NONE;    /* initialization done */int     pciConfigMech = NONE;       /* 1=mechanism-1, 2=mechanism-2 */int     pciMaxBus = PCI_MAX_BUS;    /* Max number of sub-busses *//* Bottom-half status variables */UINT last_dstatus = 0x0;UINT last_isr_status = 0x0;UINT total_dma_disabled_errs = 0x0;UINT total_sync_errs = 0x0;UINT total_abort_errs = 0x0;UINT total_dma_errs = 0x0;UINT total_parity_errs = 0x0;UINT total_bus_parity_errs = 0x0;UINT total_fifo_overrun_errs = 0x0;UINT total_fifo_resync_errs = 0x0;UINT total_bus_latency_errs = 0x0;UINT total_risc_ints = 0x0;UINT total_ints = 0x0;UINT total_write_tags = 0x0;UINT total_skip_tags = 0x0;UINT total_jump_tags = 0x0;UINT total_sync_tags = 0x0;/* Bottom-half control-monitor variables */int	btvid_tid;int     stream_tid;int	frame_acq_cnt = 0;int	current_frame = 1;SEM_ID frameRdy;SEM_ID streamRdy;#include "msgQLib.h"#include "mqueue.h"#include "errnoLib.h" #include "ioLib.h" #define SNDRCV_MQ "send_frame_mq"#define MAX_MSG_SIZE 4struct mq_attr mq_attr;enum devices {	NORTH_BRIDGE,	SOUTH_BRIDGE,	MONITOR_VIDEO_CARD,	CAPTURE_VIDEO_CARD,	NUMDEVICES};typedef struct _PCI_DEVICE_BUS_NAME {	int venId;    	int devId;  /* device ID */    	int index;     /* desired instance of device */    	int busNo;    /* bus number */    	int deviceNo; /* device number */    	int funcNo;   /* function number */} PCI_DEV_BUS_NAME;PCI_DEV_BUS_NAME PCI_DEV[NUMDEVICES];STATUS findBusDevFunNo(void) {		int i = 0;	STATUS temp;		for(i = 0; i < NUMDEVICES; i++)		temp = pciFindDevice(					PCI_DEV[i].venId, 				PCI_DEV[i].devId,				PCI_DEV[i].index,				&(PCI_DEV[i].busNo),				&(PCI_DEV[i].deviceNo),				&(PCI_DEV[i].funcNo)			     );	return temp;}STATUS initializePCI_DEV(void) {	int i = 0;		for(i = 0; i < NUMDEVICES; i++) {				PCI_DEV[i].venId = 0;		PCI_DEV[i].devId = 0;		PCI_DEV[i].index = 0;		PCI_DEV[i].busNo = 0;		PCI_DEV[i].deviceNo = 0;		PCI_DEV[i].funcNo = 0;	}	/* Add Specfic Devices Here */	PCI_DEV[NORTH_BRIDGE].venId = 0x8086; 	PCI_DEV[NORTH_BRIDGE].devId = 0x1237; 	PCI_DEV[NORTH_BRIDGE].index = 0x0;		PCI_DEV[SOUTH_BRIDGE].venId = 0x8086; 	PCI_DEV[SOUTH_BRIDGE].devId = 0x7000; 	PCI_DEV[SOUTH_BRIDGE].index = 0x0;		PCI_DEV[MONITOR_VIDEO_CARD].venId = 0x5333; 	PCI_DEV[MONITOR_VIDEO_CARD].devId = 0x8a01; 	PCI_DEV[MONITOR_VIDEO_CARD].index = 0x0;		PCI_DEV[CAPTURE_VIDEO_CARD].venId = 0x109e; 	PCI_DEV[CAPTURE_VIDEO_CARD].devId = 0x036e; 	PCI_DEV[CAPTURE_VIDEO_CARD].index = 0x0;	findBusDevFunNo();	return OK;}STATUS findBusNames(void) {		int i = 0;	STATUS temp;		for(i = 0; i < NUMDEVICES; i++)		temp = pciFindDevice(					PCI_DEV[i].venId, 				PCI_DEV[i].devId,				PCI_DEV[i].index,				&(PCI_DEV[i].busNo),				&(PCI_DEV[i].deviceNo),				&(PCI_DEV[i].funcNo)