--  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,--  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.--  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,--  OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;--  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT--  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.--  --  --  Overview:--  --    Performs a radix 2 Fast Fourier Transform.--    The FFT architecture is pipelined on a rank basis; each rank has its own butterfly and ranks are--    isolated from each other using memory interleavers.  This FFT can perform calcualations on continuous--    streaming data (one data set right after another).  More over, inputs and outputs are passed in pairs,--    doubling the bandwidth.  For instance, a 2048 point FFT can perform a transform every 1024 cycles.--  --  Interface:--  --    Synchronization:--      clock_c  : Clock input.--      enable_i : Synchronous enable.--      reset_i  : Synchronous reset.--  --    Inputs:--      sync_i     : Input sync pulse must occur one frame prior to data input.--      data_0_i   : Input data 0.  Width is 2 * precision.  Real on the left, imag on the right.--      data_1_i   : Input data 1.  Width is 2 * precision.  Real on the left, imag on the right.--  --    Outputs:--      sync_o     : Output sync pulse occurs one frame before data output.--      data_0_o   : Output data 0.  Width is 2 * precision.  Real on the left, imag on the right.--      data_1_o   : Output data 1.  Width is 2 * precision.  Real on the left, imag on the right.--  --  Built In Parameters:--  --    FFT Points   = 1024--    Precision    = 16--  --  --  --  --  Generated by Confluence 0.6.3  --  Launchbird Design Systems, Inc.  --  www.launchbird.com--  --  Build Date : Fri Aug 22 08:44:00 CDT 2003--  --  Interface--  --    Build Name    : cf_fft_1024_16--    Clock Domains : clock_c  --    Vector Input  : enable_i(1)--    Vector Input  : reset_i(1)--    Vector Input  : sync_i(1)--    Vector Input  : data_0_i(32)--    Vector Input  : data_1_i(32)--    Vector Output : sync_o(1)--    Vector Output : data_0_o(32)--    Vector Output : data_1_o(32)--  --  --  library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity cf_fft_1024_16_39 isport (clock_c : in std_logic;i1 : in  unsigned(31 downto 0);i2 : in  unsigned(31 downto 0);i3 : in  unsigned(0 downto 0);i4 : in  unsigned(0 downto 0);i5 : in  unsigned(0 downto 0);o1 : out unsigned(31 downto 0);o2 : out unsigned(31 downto 0));end entity cf_fft_1024_16_39;architecture rtl of cf_fft_1024_16_39 issignal n1 : unsigned(31 downto 0) := "00000000000000000000000000000000";signal n2 : unsigned(15 downto 0);signal n3 : unsigned(15 downto 0);signal n4 : unsigned(31 downto 0) := "00000000000000000000000000000000";signal n5 : unsigned(15 downto 0);signal n6 : unsigned(15 downto 0);signal n7 : unsigned(15 downto 0) := "0000000000000000";signal n8 : unsigned(15 downto 0) := "0000000000000000";signal n9 : unsigned(15 downto 0) := "0000000000000000";signal n10 : unsigned(15 downto 0) := "0000000000000000";signal n11 : unsigned(31 downto 0) := "00000000000000000000000000000000";signal n12 : unsigned(15 downto 0);signal n13 : unsigned(15 downto 0);signal n14 : unsigned(31 downto 0);signal n15 : unsigned(15 downto 0);signal n16 : unsigned(15 downto 0) := "0000000000000000";signal n17 : unsigned(31 downto 0);signal n18 : unsigned(15 downto 0);signal n19 : unsigned(15 downto 0) := "0000000000000000";signal n20 : unsigned(15 downto 0);signal n21 : unsigned(15 downto 0) := "0000000000000000";signal n22 : unsigned(31 downto 0);signal n23 : unsigned(15 downto 0);signal n24 : unsigned(15 downto 0) := "0000000000000000";signal n25 : unsigned(31 downto 0);signal n26 : unsigned(15 downto 0);signal n27 : unsigned(15 downto 0) := "0000000000000000";signal n28 : unsigned(15 downto 0);signal n29 : unsigned(15 downto 0) := "0000000000000000";signal n30 : unsigned(15 downto 0);signal n31 : unsigned(15 downto 0);signal n32 : unsigned(31 downto 0);signal n33 : unsigned(31 downto 0) := "00000000000000000000000000000000";signal n34 : unsigned(15 downto 0);signal n35 : unsigned(15 downto 0);signal n36 : unsigned(31 downto 0);signal n37 : unsigned(31 downto 0) := "00000000000000000000000000000000";beginprocess (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n1 <= "00000000000000000000000000000000";    elsif i4 = "1" then      n1 <= i1;    end if;  end if;end process;n2 <= n1(31 downto 31) &  n1(30 downto 30) &  n1(29 downto 29) &  n1(28 downto 28) &  n1(27 downto 27) &  n1(26 downto 26) &  n1(25 downto 25) &  n1(24 downto 24) &  n1(23 downto 23) &  n1(22 downto 22) &  n1(21 downto 21) &  n1(20 downto 20) &  n1(19 downto 19) &  n1(18 downto 18) &  n1(17 downto 17) &  n1(16 downto 16);n3 <= n1(15 downto 15) &  n1(14 downto 14) &  n1(13 downto 13) &  n1(12 downto 12) &  n1(11 downto 11) &  n1(10 downto 10) &  n1(9 downto 9) &  n1(8 downto 8) &  n1(7 downto 7) &  n1(6 downto 6) &  n1(5 downto 5) &  n1(4 downto 4) &  n1(3 downto 3) &  n1(2 downto 2) &  n1(1 downto 1) &  n1(0 downto 0);process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n4 <= "00000000000000000000000000000000";    elsif i4 = "1" then      n4 <= i2;    end if;  end if;end process;n5 <= n4(31 downto 31) &  n4(30 downto 30) &  n4(29 downto 29) &  n4(28 downto 28) &  n4(27 downto 27) &  n4(26 downto 26) &  n4(25 downto 25) &  n4(24 downto 24) &  n4(23 downto 23) &  n4(22 downto 22) &  n4(21 downto 21) &  n4(20 downto 20) &  n4(19 downto 19) &  n4(18 downto 18) &  n4(17 downto 17) &  n4(16 downto 16);n6 <= n4(15 downto 15) &  n4(14 downto 14) &  n4(13 downto 13) &  n4(12 downto 12) &  n4(11 downto 11) &  n4(10 downto 10) &  n4(9 downto 9) &  n4(8 downto 8) &  n4(7 downto 7) &  n4(6 downto 6) &  n4(5 downto 5) &  n4(4 downto 4) &  n4(3 downto 3) &  n4(2 downto 2) &  n4(1 downto 1) &  n4(0 downto 0);process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n7 <= "0000000000000000";    elsif i4 = "1" then      n7 <= n2;    end if;  end if;end process;process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n8 <= "0000000000000000";    elsif i4 = "1" then      n8 <= n7;    end if;  end if;end process;process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n9 <= "0000000000000000";    elsif i4 = "1" then      n9 <= n3;    end if;  end if;end process;process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n10 <= "0000000000000000";    elsif i4 = "1" then      n10 <= n9;    end if;  end if;end process;process (clock_c) begin  if rising_edge(clock_c) then     if i4 = "1" then      case i3 is        when "0" => n11 <= "01111111111111110000000000000000";        when "1" => n11 <= "00000000000000001000000000000000";        when others => n11 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";      end case;    end if;  end if;end process;n12 <= n11(31 downto 31) &  n11(30 downto 30) &  n11(29 downto 29) &  n11(28 downto 28) &  n11(27 downto 27) &  n11(26 downto 26) &  n11(25 downto 25) &  n11(24 downto 24) &  n11(23 downto 23) &  n11(22 downto 22) &  n11(21 downto 21) &  n11(20 downto 20) &  n11(19 downto 19) &  n11(18 downto 18) &  n11(17 downto 17) &  n11(16 downto 16);n13 <= n11(15 downto 15) &  n11(14 downto 14) &  n11(13 downto 13) &  n11(12 downto 12) &  n11(11 downto 11) &  n11(10 downto 10) &  n11(9 downto 9) &  n11(8 downto 8) &  n11(7 downto 7) &  n11(6 downto 6) &  n11(5 downto 5) &  n11(4 downto 4) &  n11(3 downto 3) &  n11(2 downto 2) &  n11(1 downto 1) &  n11(0 downto 0);n14 <= unsigned(signed(n5) * signed(n12));n15 <= n14(30 downto 30) &  n14(29 downto 29) &  n14(28 downto 28) &  n14(27 downto 27) &  n14(26 downto 26) &  n14(25 downto 25) &  n14(24 downto 24) &  n14(23 downto 23) &  n14(22 downto 22) &  n14(21 downto 21) &  n14(20 downto 20) &  n14(19 downto 19) &  n14(18 downto 18) &  n14(17 downto 17) &  n14(16 downto 16) &  n14(15 downto 15);process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n16 <= "0000000000000000";    elsif i4 = "1" then      n16 <= n15;    end if;  end if;end process;n17 <= unsigned(signed(n6) * signed(n13));n18 <= n17(30 downto 30) &  n17(29 downto 29) &  n17(28 downto 28) &  n17(27 downto 27) &  n17(26 downto 26) &  n17(25 downto 25) &  n17(24 downto 24) &  n17(23 downto 23) &  n17(22 downto 22) &  n17(21 downto 21) &  n17(20 downto 20) &  n17(19 downto 19) &  n17(18 downto 18) &  n17(17 downto 17) &  n17(16 downto 16) &  n17(15 downto 15);process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n19 <= "0000000000000000";    elsif i4 = "1" then      n19 <= n18;    end if;  end if;end process;n20 <= n16 - n19;process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n21 <= "0000000000000000";    elsif i4 = "1" then      n21 <= n20;    end if;  end if;end process;n22 <= unsigned(signed(n5) * signed(n13));n23 <= n22(30 downto 30) &  n22(29 downto 29) &  n22(28 downto 28) &  n22(27 downto 27) &  n22(26 downto 26) &  n22(25 downto 25) &  n22(24 downto 24) &  n22(23 downto 23) &  n22(22 downto 22) &  n22(21 downto 21) &  n22(20 downto 20) &  n22(19 downto 19) &  n22(18 downto 18) &  n22(17 downto 17) &  n22(16 downto 16) &  n22(15 downto 15);process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n24 <= "0000000000000000";    elsif i4 = "1" then      n24 <= n23;    end if;  end if;end process;n25 <= unsigned(signed(n6) * signed(n12));n26 <= n25(30 downto 30) &  n25(29 downto 29) &  n25(28 downto 28) &  n25(27 downto 27) &  n25(26 downto 26) &  n25(25 downto 25) &  n25(24 downto 24) &  n25(23 downto 23) &  n25(22 downto 22) &  n25(21 downto 21) &  n25(20 downto 20) &  n25(19 downto 19) &  n25(18 downto 18) &  n25(17 downto 17) &  n25(16 downto 16) &  n25(15 downto 15);process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n27 <= "0000000000000000";    elsif i4 = "1" then      n27 <= n26;    end if;  end if;end process;n28 <= n24 + n27;process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n29 <= "0000000000000000";    elsif i4 = "1" then      n29 <= n28;    end if;  end if;end process;n30 <= n8 + n21;n31 <= n10 + n29;n32 <= n30 & n31;process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n33 <= "00000000000000000000000000000000";    elsif i4 = "1" then      n33 <= n32;    end if;