end if;end process;n34 <= n8 - n21;n35 <= n10 - n29;n36 <= n34 & n35;process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n37 <= "00000000000000000000000000000000";    elsif i4 = "1" then      n37 <= n36;    end if;  end if;end process;o2 <= n37;o1 <= n33;end architecture rtl;library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity cf_fft_1024_16_38 isport (i1 : in  unsigned(0 downto 0);i2 : in  unsigned(0 downto 0);i3 : in  unsigned(0 downto 0);i4 : in  unsigned(0 downto 0);i5 : in  unsigned(2 downto 0);o1 : out unsigned(0 downto 0));end entity cf_fft_1024_16_38;architecture rtl of cf_fft_1024_16_38 issignal n1 : unsigned(2 downto 0);signal n2 : unsigned(2 downto 0);signal n3 : unsigned(2 downto 0);signal n4 : unsigned(0 downto 0);signal n5 : unsigned(0 downto 0);signal n6 : unsigned(0 downto 0);signal n7 : unsigned(0 downto 0);signal n8 : unsigned(0 downto 0);signal n9 : unsigned(0 downto 0);beginn1 <= "001";n2 <= "011";n3 <= "101";n4 <= "1" when i5 = n1 else "0";n5 <= "1" when i5 = n2 else "0";n6 <= "1" when i5 = n3 else "0";n7 <= i2 when n6 = "1" else i1;n8 <= i3 when n5 = "1" else n7;n9 <= i4 when n4 = "1" else n8;o1 <= n9;end architecture rtl;library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity cf_fft_1024_16_37 isport (i1 : in  unsigned(0 downto 0);i2 : in  unsigned(0 downto 0);i3 : in  unsigned(0 downto 0);i4 : in  unsigned(0 downto 0);i5 : in  unsigned(0 downto 0);i6 : in  unsigned(0 downto 0);i7 : in  unsigned(0 downto 0);i8 : in  unsigned(2 downto 0);o1 : out unsigned(0 downto 0));end entity cf_fft_1024_16_37;architecture rtl of cf_fft_1024_16_37 issignal n1 : unsigned(2 downto 0);signal n2 : unsigned(2 downto 0);signal n3 : unsigned(2 downto 0);signal n4 : unsigned(0 downto 0);signal n5 : unsigned(0 downto 0);signal n6 : unsigned(0 downto 0);signal n7 : unsigned(0 downto 0);signal n8 : unsigned(0 downto 0);signal n9 : unsigned(0 downto 0);signal s10_1 : unsigned(0 downto 0);component cf_fft_1024_16_38 isport (i1 : in  unsigned(0 downto 0);i2 : in  unsigned(0 downto 0);i3 : in  unsigned(0 downto 0);i4 : in  unsigned(0 downto 0);i5 : in  unsigned(2 downto 0);o1 : out unsigned(0 downto 0));end component cf_fft_1024_16_38;beginn1 <= "010";n2 <= "100";n3 <= "110";n4 <= "1" when i8 = n1 else "0";n5 <= "1" when i8 = n2 else "0";n6 <= "1" when i8 = n3 else "0";n7 <= i5 when n6 = "1" else s10_1;n8 <= i6 when n5 = "1" else n7;n9 <= i7 when n4 = "1" else n8;s10 : cf_fft_1024_16_38 port map (i1, i2, i3, i4, i8, s10_1);o1 <= n9;end architecture rtl;library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity cf_fft_1024_16_36 isport (o1 : out unsigned(0 downto 0);o2 : out unsigned(0 downto 0);o3 : out unsigned(0 downto 0);o4 : out unsigned(0 downto 0);o5 : out unsigned(0 downto 0);o6 : out unsigned(0 downto 0);o7 : out unsigned(0 downto 0);o8 : out unsigned(0 downto 0));end entity cf_fft_1024_16_36;architecture rtl of cf_fft_1024_16_36 issignal n1 : unsigned(0 downto 0);signal n2 : unsigned(0 downto 0);signal n3 : unsigned(0 downto 0);signal n4 : unsigned(0 downto 0);signal n5 : unsigned(0 downto 0);signal n6 : unsigned(0 downto 0);signal n7 : unsigned(0 downto 0);signal n8 : unsigned(0 downto 0);beginn1 <= "0";n2 <= "1";n3 <= "0";n4 <= "1";n5 <= "0";n6 <= "1";n7 <= "0";n8 <= "0";o8 <= n8;o7 <= n7;o6 <= n6;o5 <= n5;o4 <= n4;o3 <= n3;o2 <= n2;o1 <= n1;end architecture rtl;library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity cf_fft_1024_16_35 isport (i1 : in  unsigned(0 downto 0);i2 : in  unsigned(0 downto 0);i3 : in  unsigned(0 downto 0);i4 : in  unsigned(2 downto 0);o1 : out unsigned(0 downto 0));end entity cf_fft_1024_16_35;architecture rtl of cf_fft_1024_16_35 issignal n1 : unsigned(2 downto 0);signal n2 : unsigned(2 downto 0);signal n3 : unsigned(2 downto 0);signal n4 : unsigned(0 downto 0);signal n5 : unsigned(0 downto 0);signal n6 : unsigned(0 downto 0);signal n7 : unsigned(0 downto 0);signal n8 : unsigned(0 downto 0);signal n9 : unsigned(0 downto 0);signal n10 : unsigned(0 downto 0);beginn1 <= "010";n2 <= "100";n3 <= "110";n4 <= "1" when i4 = n1 else "0";n5 <= "1" when i4 = n2 else "0";n6 <= "1" when i4 = n3 else "0";n7 <= i1 when n6 = "1" else n10;n8 <= i2 when n5 = "1" else n7;n9 <= i3 when n4 = "1" else n8;n10 <= "1";o1 <= n9;end architecture rtl;library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity cf_fft_1024_16_34 isport (i1 : in  unsigned(2 downto 0);o1 : out unsigned(0 downto 0));end entity cf_fft_1024_16_34;architecture rtl of cf_fft_1024_16_34 issignal n1 : unsigned(0 downto 0);signal n2 : unsigned(0 downto 0);signal n3 : unsigned(0 downto 0);signal n4 : unsigned(0 downto 0);signal n5 : unsigned(2 downto 0);signal n6 : unsigned(0 downto 0);signal n7 : unsigned(0 downto 0);signal s8_1 : unsigned(0 downto 0);component cf_fft_1024_16_35 isport (i1 : in  unsigned(0 downto 0);i2 : in  unsigned(0 downto 0);i3 : in  unsigned(0 downto 0);i4 : in  unsigned(2 downto 0);o1 : out unsigned(0 downto 0));end component cf_fft_1024_16_35;beginn1 <= "0";n2 <= "0";n3 <= "0";n4 <= "0";n5 <= "000";n6 <= "1" when i1 = n5 else "0";n7 <= n4 when n6 = "1" else s8_1;s8 : cf_fft_1024_16_35 port map (n1, n2, n3, i1, s8_1);o1 <= n7;end architecture rtl;library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity cf_fft_1024_16_33 isport (clock_c : in std_logic;i1 : in  unsigned(1 downto 0);i2 : in  unsigned(0 downto 0);i3 : in  unsigned(0 downto 0);o1 : out unsigned(0 downto 0));end entity cf_fft_1024_16_33;architecture rtl of cf_fft_1024_16_33 issignal n1 : unsigned(2 downto 0);signal n2 : unsigned(2 downto 0);signal n3 : unsigned(0 downto 0);signal n4 : unsigned(0 downto 0);signal n5 : unsigned(0 downto 0) := "0";signal s6_1 : unsigned(0 downto 0);signal s7_1 : unsigned(0 downto 0);signal s7_2 : unsigned(0 downto 0);signal s7_3 : unsigned(0 downto 0);signal s7_4 : unsigned(0 downto 0);signal s7_5 : unsigned(0 downto 0);signal s7_6 : unsigned(0 downto 0);signal s7_7 : unsigned(0 downto 0);signal s7_8 : unsigned(0 downto 0);signal s8_1 : unsigned(0 downto 0);component cf_fft_1024_16_37 isport (i1 : in  unsigned(0 downto 0);i2 : in  unsigned(0 downto 0);i3 : in  unsigned(0 downto 0);i4 : in  unsigned(0 downto 0);i5 : in  unsigned(0 downto 0);i6 : in  unsigned(0 downto 0);i7 : in  unsigned(0 downto 0);i8 : in  unsigned(2 downto 0);o1 : out unsigned(0 downto 0));end component cf_fft_1024_16_37;component cf_fft_1024_16_36 isport (o1 : out unsigned(0 downto 0);o2 : out unsigned(0 downto 0);o3 : out unsigned(0 downto 0);o4 : out unsigned(0 downto 0);o5 : out unsigned(0 downto 0);o6 : out unsigned(0 downto 0);o7 : out unsigned(0 downto 0);o8 : out unsigned(0 downto 0));end component cf_fft_1024_16_36;component cf_fft_1024_16_34 isport (i1 : in  unsigned(2 downto 0);o1 : out unsigned(0 downto 0));end component cf_fft_1024_16_34;beginn1 <= "000";n2 <= i1 & n5;n3 <= "1" when n2 = n1 else "0";n4 <= s7_8 when n3 = "1" else s6_1;process (clock_c) begin  if rising_edge(clock_c) then    if i3 = "1" then      n5 <= "0";    elsif i2 = "1" then      n5 <= n4;    end if;  end if;end process;s6 : cf_fft_1024_16_37 port map (s7_1, s7_2, s7_3, s7_4, s7_5, s7_6, s7_7, n2, s6_1);s7 : cf_fft_1024_16_36 port map (s7_1, s7_2, s7_3, s7_4, s7_5, s7_6, s7_7, s7_8);s8 : cf_fft_1024_16_34 port map (n2, s8_1);o1 <= s8_1;end architecture rtl;library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity cf_fft_1024_16_32 isport (i1 : in  unsigned(0 downto 0);i2 : in  unsigned(0 downto 0);i3 : in  unsigned(0 downto 0);i4 : in  unsigned(0 downto 0);i5 : in  unsigned(1 downto 0);o1 : out unsigned(0 downto 0));end entity cf_fft_1024_16_32;architecture rtl of cf_fft_1024_16_32 issignal n1 : unsigned(1 downto 0);signal n2 : unsigned(1 downto 0);signal n3 : unsigned(1 downto 0);signal n4 : unsigned(0 downto 0);signal n5 : unsigned(0 downto 0);signal n6 : unsigned(0 downto 0);signal n7 : unsigned(0 downto 0);signal n8 : unsigned(0 downto 0);signal n9 : unsigned(0 downto 0);beginn1 <= "00";n2 <= "10";n3 <= "01";n4 <= "1" when i5 = n1 else "0";n5 <= "1" when i5 = n2 else "0";n6 <= "1" when i5 = n3 else "0";n7 <= i2 when n6 = "1" else i1;n8 <= i3 when n5 = "1" else n7;n9 <= i4 when n4 = "1" else n8;o1 <= n9;end architecture rtl;library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity cf_fft_1024_16_31 isport (i1 : in  unsigned(1 downto 0);o1 : out unsigned(0 downto 0));end entity cf_fft_1024_16_31;architecture rtl of cf_fft_1024_16_31 issignal n1 : unsigned(0 downto 0);signal n2 : unsigned(0 downto 0);signal n3 : unsigned(1 downto 0);signal n4 : unsigned(1 downto 0);signal n5 : unsigned(0 downto 0);signal n6 : unsigned(0 downto 0);signal n7 : unsigned(0 downto 0);signal n8 : unsigned(0 downto 0);signal n9 : unsigned(0 downto 0);beginn1 <= "0";n2 <= "0";n3 <= "00";n4 <= "10";n5 <= "1" when i1 = n3 else "0";n6 <= "1" when i1 = n4 else "0";n7 <= n1 when n6 = "1" else n9;n8 <= n2 when n5 = "1" else n7;n9 <= "1";o1 <= n8;end architecture rtl;library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity cf_fft_1024_16_30 isport (clock_c : in std_logic;i1 : in  unsigned(0 downto 0);i2 : in  unsigned(0 downto 0);i3 : in  unsigned(0 downto 0);o1 : out unsigned(0 downto 0));end entity cf_fft_1024_16_30;architecture rtl of cf_fft_1024_16_30 issignal n1 : unsigned(0 downto 0);signal n2 : unsigned(0 downto 0);signal n3 : unsigned(0 downto 0);signal n4 : unsigned(0 downto 0);signal n5 : unsigned(1 downto 0);signal n6 : unsigned(0 downto 0) := "0";signal s7_1 : unsigned(0 downto 0);signal s8_1 : unsigned(0 downto 0);component cf_fft_1024_16_32 isport (i1 : in  unsigned(0 downto 0);i2 : in  unsigned(0 downto 0);i3 : in  unsigned(0 downto 0);i4 : in  unsigned(0 downto 0);i5 : in  unsigned(1 downto 0);o1 : out unsigned(0 downto 0));end component cf_fft_1024_16_32;component cf_fft_1024_16_31 isport (i1 : in  unsigned(1 downto 0);o1 : out unsigned(0 downto 0));end component cf_fft_1024_16_31;beginn1 <= "0";n2 <= "1";n3 <= "1";n4 <= "0";n5 <= i1 & n6;process (clock_c) begin  if rising_edge(clock_c) then    if i3 = "1" then      n6 <= "0";    elsif i2 = "1" then      n6 <= s7_1;    end if;  end if;end process;s7 : cf_fft_1024_16_32 port map (n1, n2, n3, n4, n5, s7_1);s8 : cf_fft_1024_16_31 port map (n5, s8_1);