n7 <= s11_1;    end if;  end if;end process;n8 <= n7 and n5;n9 <= i1 or i3;n10 <= s11_1 and i2;s11 : cf_fft_1024_16_25 port map (clock_c, n6, i2, i3, s11_1);o2 <= n8;o1 <= n3;end architecture rtl;library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity cf_fft_1024_16_23 isport (clock_c : in std_logic;i1 : in  unsigned(0 downto 0);i2 : in  unsigned(31 downto 0);i3 : in  unsigned(31 downto 0);i4 : in  unsigned(0 downto 0);i5 : in  unsigned(0 downto 0);o1 : out unsigned(0 downto 0);o2 : out unsigned(31 downto 0);o3 : out unsigned(31 downto 0));end entity cf_fft_1024_16_23;architecture rtl of cf_fft_1024_16_23 issignal n1 : unsigned(0 downto 0);signal n2 : unsigned(63 downto 0);signal n3 : unsigned(0 downto 0) := "0";signal n4 : unsigned(0 downto 0) := "0";signal n5 : unsigned(0 downto 0) := "0";signal n6 : unsigned(0 downto 0) := "0";signal n7 : unsigned(7 downto 0);signal n8 : unsigned(7 downto 0) := "00000000";signal n9 : unsigned(7 downto 0) := "00000000";signal n10 : unsigned(7 downto 0) := "00000000";signal n11 : unsigned(7 downto 0) := "00000000";signal n12 : unsigned(0 downto 0);signal n13 : unsigned(0 downto 0) := "0";signal n14 : unsigned(0 downto 0) := "0";signal n15 : unsigned(0 downto 0) := "0";signal n16 : unsigned(0 downto 0) := "0";signal n17 : unsigned(0 downto 0);signal n18 : unsigned(1 downto 0);signal n19 : unsigned(31 downto 0);signal n20 : unsigned(31 downto 0);signal n21 : unsigned(31 downto 0);signal n22 : unsigned(31 downto 0);signal n23 : unsigned(31 downto 0);signal n24 : unsigned(31 downto 0);signal s25_1 : unsigned(31 downto 0);signal s25_2 : unsigned(31 downto 0);signal s26_1 : unsigned(0 downto 0);signal s27_1 : unsigned(63 downto 0);signal s28_1 : unsigned(0 downto 0);signal s28_2 : unsigned(0 downto 0);signal s28_3 : unsigned(63 downto 0);signal s29_1 : unsigned(8 downto 0);signal s29_2 : unsigned(0 downto 0);component cf_fft_1024_16_39 isport (clock_c : in std_logic;i1 : in  unsigned(31 downto 0);i2 : in  unsigned(31 downto 0);i3 : in  unsigned(0 downto 0);i4 : in  unsigned(0 downto 0);i5 : in  unsigned(0 downto 0);o1 : out unsigned(31 downto 0);o2 : out unsigned(31 downto 0));end component cf_fft_1024_16_39;component cf_fft_1024_16_33 isport (clock_c : in std_logic;i1 : in  unsigned(1 downto 0);i2 : in  unsigned(0 downto 0);i3 : in  unsigned(0 downto 0);o1 : out unsigned(0 downto 0));end component cf_fft_1024_16_33;component cf_fft_1024_16_29 isport (clock_c : in std_logic;i1 : in  unsigned(63 downto 0);i2 : in  unsigned(0 downto 0);i3 : in  unsigned(7 downto 0);i4 : in  unsigned(0 downto 0);i5 : in  unsigned(0 downto 0);i6 : in  unsigned(0 downto 0);o1 : out unsigned(63 downto 0));end component cf_fft_1024_16_29;component cf_fft_1024_16_28 isport (clock_c : in std_logic;i1 : in  unsigned(63 downto 0);i2 : in  unsigned(0 downto 0);i3 : in  unsigned(7 downto 0);i4 : in  unsigned(0 downto 0);i5 : in  unsigned(0 downto 0);i6 : in  unsigned(0 downto 0);o1 : out unsigned(0 downto 0);o2 : out unsigned(0 downto 0);o3 : out unsigned(63 downto 0));end component cf_fft_1024_16_28;component cf_fft_1024_16_24 isport (clock_c : in std_logic;i1 : in  unsigned(0 downto 0);i2 : in  unsigned(0 downto 0);i3 : in  unsigned(0 downto 0);o1 : out unsigned(8 downto 0);o2 : out unsigned(0 downto 0));end component cf_fft_1024_16_24;beginn1 <= s29_1(8 downto 8);n2 <= s25_1 & s25_2;process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n3 <= "0";    elsif i4 = "1" then      n3 <= s29_2;    end if;  end if;end process;process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n4 <= "0";    elsif i4 = "1" then      n4 <= n3;    end if;  end if;end process;process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n5 <= "0";    elsif i4 = "1" then      n5 <= n4;    end if;  end if;end process;process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n6 <= "0";    elsif i4 = "1" then      n6 <= n5;    end if;  end if;end process;n7 <= s29_1(8 downto 8) &  s29_1(7 downto 7) &  s29_1(6 downto 6) &  s29_1(5 downto 5) &  s29_1(4 downto 4) &  s29_1(3 downto 3) &  s29_1(2 downto 2) &  s29_1(1 downto 1);process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n8 <= "00000000";    elsif i4 = "1" then      n8 <= n7;    end if;  end if;end process;process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n9 <= "00000000";    elsif i4 = "1" then      n9 <= n8;    end if;  end if;end process;process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n10 <= "00000000";    elsif i4 = "1" then      n10 <= n9;    end if;  end if;end process;process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n11 <= "00000000";    elsif i4 = "1" then      n11 <= n10;    end if;  end if;end process;n12 <= s29_1(0 downto 0);process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n13 <= "0";    elsif i4 = "1" then      n13 <= n12;    end if;  end if;end process;process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n14 <= "0";    elsif i4 = "1" then      n14 <= n13;    end if;  end if;end process;process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n15 <= "0";    elsif i4 = "1" then      n15 <= n14;    end if;  end if;end process;process (clock_c) begin  if rising_edge(clock_c) then    if i5 = "1" then      n16 <= "0";    elsif i4 = "1" then      n16 <= n15;    end if;  end if;end process;n17 <= not n16;n18 <= s28_2 & s28_1;n19 <= s28_3(63 downto 63) &  s28_3(62 downto 62) &  s28_3(61 downto 61) &  s28_3(60 downto 60) &  s28_3(59 downto 59) &  s28_3(58 downto 58) &  s28_3(57 downto 57) &  s28_3(56 downto 56) &  s28_3(55 downto 55) &  s28_3(54 downto 54) &  s28_3(53 downto 53) &  s28_3(52 downto 52) &  s28_3(51 downto 51) &  s28_3(50 downto 50) &  s28_3(49 downto 49) &  s28_3(48 downto 48) &  s28_3(47 downto 47) &  s28_3(46 downto 46) &  s28_3(45 downto 45) &  s28_3(44 downto 44) &  s28_3(43 downto 43) &  s28_3(42 downto 42) &  s28_3(41 downto 41) &  s28_3(40 downto 40) &  s28_3(39 downto 39) &  s28_3(38 downto 38) &  s28_3(37 downto 37) &  s28_3(36 downto 36) &  s28_3(35 downto 35) &  s28_3(34 downto 34) &  s28_3(33 downto 33) &  s28_3(32 downto 32);n20 <= s28_3(31 downto 31) &  s28_3(30 downto 30) &  s28_3(29 downto 29) &  s28_3(28 downto 28) &  s28_3(27 downto 27) &  s28_3(26 downto 26) &  s28_3(25 downto 25) &  s28_3(24 downto 24) &  s28_3(23 downto 23) &  s28_3(22 downto 22) &  s28_3(21 downto 21) &  s28_3(20 downto 20) &  s28_3(19 downto 19) &  s28_3(18 downto 18) &  s28_3(17 downto 17) &  s28_3(16 downto 16) &  s28_3(15 downto 15) &  s28_3(14 downto 14) &  s28_3(13 downto 13) &  s28_3(12 downto 12) &  s28_3(11 downto 11) &  s28_3(10 downto 10) &  s28_3(9 downto 9) &  s28_3(8 downto 8) &  s28_3(7 downto 7) &  s28_3(6 downto 6) &  s28_3(5 downto 5) &  s28_3(4 downto 4) &  s28_3(3 downto 3) &  s28_3(2 downto 2) &  s28_3(1 downto 1) &  s28_3(0 downto 0);n21 <= s27_1(63 downto 63) &  s27_1(62 downto 62) &  s27_1(61 downto 61) &  s27_1(60 downto 60) &  s27_1(59 downto 59) &  s27_1(58 downto 58) &  s27_1(57 downto 57) &  s27_1(56 downto 56) &  s27_1(55 downto 55) &  s27_1(54 downto 54) &  s27_1(53 downto 53) &  s27_1(52 downto 52) &  s27_1(51 downto 51) &  s27_1(50 downto 50) &  s27_1(49 downto 49) &  s27_1(48 downto 48) &  s27_1(47 downto 47) &  s27_1(46 downto 46) &  s27_1(45 downto 45) &  s27_1(44 downto 44) &  s27_1(43 downto 43) &  s27_1(42 downto 42) &  s27_1(41 downto 41) &  s27_1(40 downto 40) &  s27_1(39 downto 39) &  s27_1(38 downto 38) &  s27_1(37 downto 37) &  s27_1(36 downto 36) &  s27_1(35 downto 35) &  s27_1(34 downto 34) &  s27_1(33 downto 33) &  s27_1(32 downto 32);n22 <= s27_1(31 downto 31) &  s27_1(30 downto 30) &  s27_1(29 downto 29) &  s27_1(28 downto 28) &  s27_1(27 downto 27) &  s27_1(26 downto 26) &  s27_1(25 downto 25) &  s27_1(24 downto 24) &  s27_1(23 downto 23) &  s27_1(22 downto 22) &  s27_1(21 downto 21) &  s27_1(20 downto 20) &  s27_1(19 downto 19) &  s27_1(18 downto 18) &  s27_1(17 downto 17) &  s27_1(16 downto 16) &  s27_1(15 downto 15) &  s27_1(14 downto 14) &  s27_1(13 downto 13) &  s27_1(12 downto 12) &  s27_1(11 downto 11) &  s27_1(10 downto 10) &  s27_1(9 downto 9) &  s27_1(8 downto 8) &  s27_1(7 downto 7) &  s27_1(6 downto 6) &  s27_1(5 downto 5) &  s27_1(4 downto 4) &  s27_1(3 downto 3) &  s27_1(2 downto 2) &  s27_1(1 downto 1) &  s27_1(0 downto 0);n23 <= n20 when s26_1 = "1" else n19;n24 <= n22 when s26_1 = "1" else n21;s25 : cf_fft_1024_16_39 port map (clock_c, i2, i3, n1, i4, i5, s25_1, s25_2);s26 : cf_fft_1024_16_33 port map (clock_c, n18, i4, i5, s26_1);s27 : cf_fft_1024_16_29 port map (clock_c, n2, n6, n11, n16, i4, i5, s27_1);s28 : cf_fft_1024_16_28 port map (clock_c, n2, n6, n11, n17, i4, i5, s28_1, s28_2, s28_3);s29 : cf_fft_1024_16_24 port map (clock_c, i1, i4, i5, s29_1, s29_2);o3 <= n24;o2 <= n23;o1 <= s28_1;end architecture rtl;library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity cf_fft_1024_16_22 isport (clock_c : in std_logic;i1 : in  unsigned(31 downto 0);i2 : in  unsigned(31 downto 0);i3 : in  unsigned(8 downto 0);i4 : in  unsigned(0 downto 0);i5 : in  unsigned(0 downto 0);o1 : out unsigned(31 downto 0);o2 : out unsigned(31 downto 0));end entity cf_fft_1024_16_22;architecture rtl of cf_fft_1024_16_22 issignal n1 : unsigned(31 downto 0) := "00000000000000000000000000000000";signal n2 : unsigned(15 downto 0);signal n3 : unsigned(15 downto 0);signal n4 : unsigned(31 downto 0) := "00000000000000000000000000000000";signal n5 : unsigned(15 downto 0);signal n6 : unsigned(15 downto 0);signal n7 : unsigned(15 downto 0) := "0000000000000000";signal n8 : unsigned(15 downto 0) := "0000000000000000";signal n9 : unsigned(15 downto 0) := "0000000000000000";signal n10 : unsigned(15 downto 0) := "0000000000000000";signal n11 : unsigned(31 downto 0) := "00000000000000000000000000000000";signal n12 : unsigned(15 downto 0);signal n13 : unsigned(15 downto 0);signal n14 : unsigned(31 downto 0);signal n15 : unsigned(15 downto 0);signal n16 : unsigned(15 downto 0) := "0000000000000000";signal n17 : unsigned(31 downto 0);signal n18 : unsigned(15 downto 0);signal n19 : unsigned(15 downto 0) := "0000000000000000";